Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A system includes a mask. The system further includes a pellicle frame attached to the mask. The pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. The pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. The system further includes a gasket within the single recess.

Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.

Abstract: A pellicle for an extreme ultraviolet (EUV) photomask includes a pellicle frame and a main membrane attached to the pellicle frame. The main membrane includes a plurality of nanotubes, and each of the plurality of nanotubes is covered by a coating layer containing Si and one or more metal elements.

Abstract: An electronic device includes a first component and a second component. The first component includes a first housing and a protrusion element. The first housing has a first cover plate, and the protrusion element is disposed on the first cover plate. The second component is rotationally assembled with the first component along a first direction. The second component includes a second housing, an elastic structure, and a switching element. The elastic structure has an elastic post. The second housing has a second cover plate having a through hole. One part of the elastic post passes through the through hole and is exposed on the second cover plate. The protrusion element moves along a first direction relative to the elastic structure, such that the elastic post is squeezed by the protrusion element to move along a second direction and presses the switching element.

Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.

Abstract: A power converter to supply power to each phase of a three-phase motor includes a booster circuit connected to a DC power supply to boost an input voltage input from the DC power supply in response to a pulse width modulation boosting signal, an inverter connected to the booster circuit and including a three-phase switching circuit including switches, and an output connected to the three-phase switching circuit to supply power to each phase of the three-phase motor, and a controller to output the pulse width modulation boosting signal to the booster circuit and output the pulse width modulation boosting signal to the booster circuit when detecting that the booster circuit is in a boosted state.

Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.

Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.

Abstract: Disclosed is an IC voltage determining method including: executing a static timing analysis according to a circuit design to obtain data of a critical path and then generating a netlist; executing a circuit parameter simulation and Monte Carlo simulation with the netlist according to a regular voltage and prescribed parameters to obtain a circuit parameter reference value and a variance of circuit parameter values; executing an adaptive voltage scaling analysis according to a voltage range to obtain a voltage-versus-parameter relation indicative of the number of times that each of circuit parameter deviations that are respectively associated with predetermined voltages within the predetermined voltage range is of the variance; and testing an IC according to the regular voltage to obtain a circuit parameter test value and determining the IC voltage according to the voltage-versus-parameter relation and a difference between the circuit parameter test value and the circuit parameter reference value.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.

Abstract: A mixer for mixing and degassing fluids includes a revolution device having a revolution base to be driven for rotation; a first spin device connected to the revolution base of the revolution device; a first barrel connected to the first spin device to be spun by the first spin device; an transmitting coil electrically connected to a power source to generate a time-vary magnetic field; and a receiving coil connected to the revolution base of the revolution device and electrically connected to the first spin device, wherein the receiving coil rotates with the revolution base. The receiving coil receives the power from the time-vary magnetic field of the transmitting coil and produces an electromotive force to be supplied to the first spin device.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: A single-gate non-volatile memory and an operation method thereof are disclosed, wherein the non-volatile memory has a single floating gate. The non-volatile memory disposes a transistor and a capacitor structure in a semiconductor substrate. The transistor has two ion-doped regions disposed at two sides of a conduction gate to function as a source and a drain and disposed in the semiconductor substrate. The widths of the source and the drain are differently, and the edge of the drain is utilized to serve as a capacitor to control the floating gate. The minimum control voltages and elements during writing are involved to greatly reduce the area, control lines and the cost thereof.