Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.

Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

Abstract: A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at two sides of the gate structure, and a boron-rich interface layer. The boron-rich interface layer includes a bottom-and-sidewall portion and a top portion, and the epitaxial source/drain structure is enclosed by the bottom-and-sidewall portion and the top portion.

Abstract: The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.

Abstract: A light-mixing module includes a first plate, a second plate, a first dichroic mirror, a second dichroic mirror, and a third dichroic mirror. The first dichroic mirror is disposed between the first plate and the second plate and is substantially perpendicular to the first plate and the second plate. The second dichroic mirror is disposed on a first side of the first dichroic mirror. The second dichroic mirror forms an angle with the first dichroic mirror and is substantially perpendicular to the first plate and the second plate. The third dichroic mirror is disposed on a second side of the first dichroic mirror and is substantially perpendicular to the first plate and the second plate. The third dichroic mirror is substantially parallel with the second dichroic mirror. The second dichroic mirror and the third dichroic mirror together form a fourth dichroic mirror, and at least one of the first dichroic mirror and the fourth dichroic mirror has a bevel gradient dichroic film.

Abstract: A system for monitoring radiation intensity of electromagnetic wave of a mobile phone has a systematic part which includes an antenna duplexer, a central processing unit, a radio frequency processing unit disposed between the antenna duplexer and the central processing unit, a power amplify circuit connected between the central processing unit and the antenna duplexer, and a systematic power source connected with the central processing unit and the power amplify circuit. A power monitor unit connected with the systematic part is capable of monitoring a power or a current of the systematic part and comparing the power or the current with a standard power or a standard current to produce a state signal. A light-emitting control circuit connected with the power monitor unit and a display device receives the state signal from the power monitor unit and drives the display device to show information corresponding to the state signal.

Abstract: The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the removal of substance containing carbon or oxygen may be performed after the oxide liner and the silicon nitride liner are formed on the bottom surface of the shallow trench. The present invention also discloses a process of treating bottom surface of the shallow trench. After the bottom surface of the shallow trench is treated, the bubble defects due to the use of the silicon nitride liner can be avoided.

Abstract: A laser module including a light emitter, a polarizing and filtering unit, a nonlinear optical crystal, and a first filter is provided. The light emitter emits a first beam. The polarizing and filtering unit is disposed on a transmission path of the first beam. A part of the first beam passes through the polarizing and filtering unit to become a second beam with a specific polarization direction. The nonlinear optical crystal is disposed on a transmission path of the second beam from the polarizing and filtering unit. The nonlinear optical crystal converts a part of the second beam into a third beam. The first filter is disposed on a transmission path of a non-converted part of the second beam and the third beam from the nonlinear optical crystal. The non-converted part of the second beam is reflected by the first filter. The third beam passes through the first filter.

Abstract: A laser module including a light emitter, a polarizing and filtering unit, a nonlinear optical crystal, and a first filter is provided. The light emitter emits a first beam. The polarizing and filtering unit is disposed on a transmission path of the first beam. A part of the first beam passes through the polarizing and filtering unit to become as a second beam with a specific polarization direction. The nonlinear optical crystal is disposed on a transmission path of the second beam from the polarizing and filtering unit. The nonlinear optical crystal converts a part of the second beam into a third beam. The first filter is disposed on a transmission path of the other part of the second beam and the third beam from the nonlinear optical crystal. The other part of the second beam is reflected by the first filter. The third beam passes through the first filter.

Abstract: The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the removal of substance containing carbon or oxygen may be performed after the oxide liner and the silicon nitride liner are formed on the bottom surface of the shallow trench. The present invention also discloses a process of treating bottom surface of the shallow trench. After the bottom surface of the shallow trench is treated, the bubble defects due to the use of the silicon nitride liner can be avoided.

Abstract: A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within a CVD reactor is carried out to deposit a low-k dielectric film stack on the first dielectric barrier until thickness of the low-k dielectric film stack reaches a desired value, wherein each of the CVD cycles comprises: (1) chemical vapor depositing a low-k dielectric film having a pre-selected thickness; and (2) cooling down the low-k dielectric film within the CVD reactor. A second damascened copper interconnect structure is formed in the low-k dielectric film stack.

Abstract: A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the vias, the conductors, and the second pad connects in series to form a chain circuit, and the first pad and the second pad are positioned at two ends of the chain circuit. A Kelvin structure is composed of the third pad, the fourth pad, one of the conductors, one of the vias, and one of the electronic components.

Abstract: A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the vias, the conductors, and the second pad connects in series to form a chain circuit, and the first pad and the second pad are positioned at two ends of the chain circuit. A Kelvin structure is composed of the third pad, the fourth pad, one of the conductors, one of the vias, and one of the electronic components.

Abstract: The present invention is related to a method for patching a firmware in a memory device. At least one functional patching program is stored at a read/write memory location inside the memory device, thereby correcting or updating a functional program in the firmware. Once the function is used, it can be directly replaced by the program stored in the memory location without re-burning or replacing the whole firmware so that the purposes of reducing cost and simplifying update firmware can be achieved.

Abstract: A method for forming an adhesion between dielectric layers, it includes forming a first dielectric layer and forming a second dielectric layer having a first portion and a second portion. The first portion is on the first dielectric layer and the second portion is on the first portion. The first portion and second portion are formed by an in-situ method. The first portion has at least one of the following a dielectric constant, hardness or SiCH3/SiO area ratio, which is higher than the second portion. A structure of enhanced-inter-adhesion dielectric layers includes a first dielectric layer and a second dielectric layer having a first portion on the first dielectric layer, and a second portion on the first portion. Herein, the first portion has a dielectric constant around 2.8 to 3.5 higher than second portion.

Abstract: A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within a CVD reactor is carried out to deposit a low-k dielectric film stack on the first dielectric barrier until thickness of the low-k dielectric film stack reaches a desired value, wherein each of the CVD cycles comprises: (1) chemical vapor depositing a low-k dielectric film having a pre-selected thickness; and (2) cooling down the low-k dielectric film within the CVD reactor.