Patents by Inventor Hsin-Chen Chen

Hsin-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12566463
    Abstract: A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.
    Type: Grant
    Filed: September 16, 2024
    Date of Patent: March 3, 2026
    Assignee: MediaTek Inc.
    Inventors: Anshul Varma, Hsin-Chen Chen
  • Patent number: 12512843
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: December 30, 2025
    Assignee: MediaTek Inc.
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Publication number: 20250335018
    Abstract: The voltage scaling system may include an oscillator, a power management unit, a frequency meter, a table unit, and a control unit. The oscillator may generate a clock signal based on a code and a power signal. The power management unit may produce the power signal from a first control signal corresponding to a requested voltage. The frequency meter may measure the clock signal frequency and may generate a second control signal. The table unit may create a maximum code. The control unit may generate the code and first control signal based on the second control signal, the maximum code, and a target frequency. The frequency of the clock signal is higher when the code is larger. The code may increase to reach a maximum value corresponding to a highest allowable operation frequency.
    Type: Application
    Filed: July 4, 2025
    Publication date: October 30, 2025
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Hsin-Chen Chen, Ashish Kumar Nayak
  • Patent number: 12375088
    Abstract: A voltage scaling system can include an oscillator, a power management unit, a frequency meter, a table unit and a control unit. The oscillator is used to generate a clock signal according to a code and a power signal. The power management unit is used to generate the power signal according to a first control signal corresponding to a requested voltage. The frequency meter is used to measure a frequency of the clock signal and generate a second control signal accordingly. The table unit is used to generate a minimum code. The control unit is used to generate the code and the first control signal according to the second control signal, the minimum code and a target frequency.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: July 29, 2025
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Hsin-Chen Chen, Ashish Kumar Nayak
  • Publication number: 20250093896
    Abstract: A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.
    Type: Application
    Filed: September 16, 2024
    Publication date: March 20, 2025
    Inventors: Anshul Varma, Hsin-Chen Chen
  • Publication number: 20240146316
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Publication number: 20240072808
    Abstract: A voltage scaling system can include an oscillator, a power management unit, a frequency meter, a table unit and a control unit. The oscillator is used to generate a clock signal according to a code and a power signal. The power management unit is used to generate the power signal according to a first control signal corresponding to a requested voltage. The frequency meter is used to measure a frequency of the clock signal and generate a second control signal accordingly. The table unit is used to generate a minimum code. The control unit is used to generate the code and the first control signal according to the second control signal, the minimum code and a target frequency.
    Type: Application
    Filed: September 9, 2022
    Publication date: February 29, 2024
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Hsin-Chen Chen, Ashish Kumar Nayak
  • Patent number: 11673166
    Abstract: A seed imaging system for imaging seeds includes a seed transfer station configured to move seeds through the system. An imaging assembly includes a first camera mounted relative to the seed transfer station and configured to acquire images of the seeds as the seeds move through the system. A second camera is mounted relative to the seed transfer station and is configured to acquire images of the seeds as the seeds move through the system. The second camera has an imaging modality different from an imaging modality of the first camera. First and second cameras may be disposed above and below the seed transfer stations, such as a transparent belt.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 13, 2023
    Assignee: Monsanto Technology LLC
    Inventors: Eric L. Borrowman, Govind Chaudhary, Hsin-Chen Chen, Jeffrey L. Kohne, Johnny J. Kotyk, Louis M. Pompe van Meerdevoort, Randall K. Rader, Brad D. White, Chi Zhang
  • Patent number: 11324968
    Abstract: A system and method for validating the accuracy of delineated contours in computerized imaging using statistical data for generating assessment criterion that define acceptable tolerances for delineated contours, with the statistical data being conditionally updated and/or refined between individual processes for validating delineated contours to thereby adjust the tolerances defined by the assessment criterion in the stored statistical data, such that the stored statistical data is more closely representative of a target population. In an alternative embodiment, a system and method for validating the accuracy of delineated contours in computerized imaging using machine learning for assessing delineated contours, with the machine learning training data being used to generate geometric attributes, and the geometric attributes used to construct intra- and interstructural geometric attribute distribution models to automatically detect contouring errors.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 10, 2022
    Assignee: Washington University
    Inventors: Hsin-Chen Chen, Sasa Mutic, Jun Tan, Michael Altman, James Kavanaugh, Hua Li
  • Patent number: 11055061
    Abstract: A signal transmission method and a circuit structure for heterogeneous platforms are provided. The method includes: adjusting signal transmission bandwidths between a first platform and a bridge circuit and between the bridge circuit and a second platform according to signal transmission speeds between the first platform and the bridge circuit and between the bridge circuit and the second platform; transmitting a command signal from the first platform to the bridge circuit and saving the command signal at a buffer of the bridge circuit; reading the command signal at the buffer of the bridge circuit by the second platform; transmitting data to the buffer of the bridge according to the command signal by the second platform; acquiring the data at the buffer of the bridge by the first platform.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 6, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Sa-Chia Ho, Hong-Chang Wu, Hsin-Chen Chen, Yi-Hsuan Wu
  • Patent number: 11044843
    Abstract: A method of analyzing seeds including acquiring, using an X-ray machine, X-ray images of the seeds. Analyzing the X-ray images to determine a parameter of each of the seeds. Comparing a parameter determined from analyzing the X-ray image of one seed to a parameter determined from analyzing the X-ray image of another seed. Arranging the seeds relative to each other based on the seed parameters.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 29, 2021
    Assignee: Monsanto Technology LLC
    Inventors: Johnny J. Kotyk, Hsin-Chen Chen
  • Publication number: 20200218504
    Abstract: A signal transmission method and a circuit structure for heterogeneous platforms are provided. The method includes: adjusting signal transmission bandwidths between a first platform and a bridge circuit and between the bridge circuit and a second platform according to signal transmission speeds between the first platform and the bridge circuit and between the bridge circuit and the second platform; transmitting a command signal from the first platform to the bridge circuit and saving the command signal at a buffer of the bridge circuit; reading the command signal at the buffer of the bridge circuit by the second platform; transmitting data to the buffer of the bridge according to the command signal by the second platform; acquiring the data at the buffer of the bridge by the first platform.
    Type: Application
    Filed: October 10, 2019
    Publication date: July 9, 2020
    Inventors: SA-CHIA HO, HONG-CHANG WU, HSIN-CHEN CHEN, YI-HSUAN WU
  • Publication number: 20200210534
    Abstract: An integrated circuitry development system includes an integrated circuitry and a programmable circuitry. The programmable circuitry is configured to execute a function of a hardware circuit to be added to the integrated circuitry. The integrated circuitry includes a memory and a first circuit. The memory is configured to store a computer program code, in which the computer program code includes a first part and a second part. The first circuit and the programmable circuitry are configured to execute the first part and the second part of the computer program code, respectively, in order to generate a simulation result for verifying at least one of the function of the hardware circuit and the second part of the computer program code.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Chihtung CHEN, Sa-Chia Ho, Hong-Chang Wu, Hsin-Chen Chen
  • Publication number: 20190314644
    Abstract: A system and method for validating the accuracy of delineated contours in computerized imaging using statistical data for generating assessment criterion that define acceptable tolerances for delineated contours, with the statistical data being conditionally updated and/or refined between individual processes for validating delineated contours to thereby adjust the tolerances defined by the assessment criterion in the stored statistical data, such that the stored statistical data is more closely representative of a target population. In an alternative embodiment, a system and method for validating the accuracy of delineated contours in computerized imaging using machine learning for assessing delineated contours, with the machine learning training data being used to generate geometric attributes, and the geometric attributes used to construct intra- and interstructural geometric attribute distribution models to automatically detect contouring errors.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventors: Hsin-Chen Chen, Sasa Mutic, Jun Tan, Michael Altman, James Kavanaugh, Hua Li
  • Publication number: 20190307055
    Abstract: A method of analyzing seeds including acquiring, using an X-ray machine, X-ray images of the seeds. Analyzing the X-ray images to determine a parameter of each of the seeds. Comparing a parameter determined from analyzing the X-ray image of one seed to a parameter determined from analyzing the X-ray image of another seed. Arranging the seeds relative to each other based on the seed parameters.
    Type: Application
    Filed: February 8, 2019
    Publication date: October 10, 2019
    Inventors: Johnny J. Kotyk, HSIN-CHEN CHEN
  • Publication number: 20190281781
    Abstract: A seed imaging system for imaging seeds includes a seed transfer station configured to move seeds through the system. An imaging assembly includes a first camera mounted relative to the seed transfer station and configured to acquire images of the seeds as the seeds move through the system. A second camera is mounted relative to the seed transfer station and is configured to acquire images of the seeds as the seeds move through the system. The second camera has an imaging modality different from an imaging modality of the first camera. First and second cameras may be disposed above and below the seed transfer stations, such as a transparent belt.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 19, 2019
    Inventors: Eric L. Borrowman, Govind Chaudhary, HSIN-CHEN CHEN, Jeffrey L. Kohne, Johnny J. Kotyk, Louis M. Pompe van Meerdevoort, Randall K. Rader, Brad D. White, Chi Zhang
  • Patent number: 10376715
    Abstract: A system and method for validating the accuracy of delineated contours in computerized imaging using statistical data for generating assessment criterion that define acceptable tolerances for delineated contours, with the statistical data being conditionally updated and/or refined between individual processes for validating delineated contours to thereby adjust the tolerances defined by the assessment criterion in the stored statistical data, such that the stored statistical data is more closely representative of a target population. In an alternative embodiment, a system and method for validating the accuracy of delineated contours in computerized imaging using machine learning for assessing delineated contours, with the machine learning training data being used to generate geometric attributes, and the geometric attributes used to construct intra- and interstructural geometric attribute distribution models to automatically detect contouring errors.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 13, 2019
    Assignee: Washington University
    Inventors: Hsin-Chen Chen, Sasa Mutic, Jun Tan, Michael Altman, James Kavanaugh, Hua Li
  • Patent number: 10345882
    Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: July 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Huajun Wen, Hugh Thomas Mair, Hsin-Chen Chen, Brian King Flachs
  • Publication number: 20160291068
    Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
    Type: Application
    Filed: November 5, 2015
    Publication date: October 6, 2016
    Inventors: Huajun Wen, Hugh Thomas Mair, Hsin-Chen Chen, Brian King Flachs
  • Publication number: 20150297916
    Abstract: A system and method for validating the accuracy of delineated contours in computerized imaging using statistical data for generating assessment criterion that define acceptable tolerances for delineated contours, with the statistical data being conditionally updated and/or refined between individual processes for validating delineated contours to thereby adjust the tolerances defined by the assessment criterion in the stored statistical data, such that the stored statistical data is more closely representative of a target population. In an alternative embodiment, a system and method for validating the accuracy of delineated contours in computerized imaging using machine learning for assessing delineated contours, with the machine learning training data being used to generate geometric attributes, and the geometric attributes used to construct intra- and interstructural geometric attribute distribution models to automatically detect contouring errors.
    Type: Application
    Filed: April 30, 2015
    Publication date: October 22, 2015
    Inventors: Hsin-Chen Chen, Sasa Mutic, Jun Tan, Michael Altman, James Kavanaugh, Hua Li