Patents by Inventor Hsin-Chen Tsai

Hsin-Chen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250088782
    Abstract: A cushion for a wearable device includes an outer cover layer and an inner cushion. The outer cover layer includes a first base material, a heat conducting material and a first heat storage material. The heat conducting material and the first heat storage material are dispersed in the first base material. The enthalpy value of the outer cover layer is less than or equal to 5 J/g. The inner cushion includes a second base material and a second heat storage material. The second heat storage material is dispersed in the second base material. The enthalpy value of the inner cushion is greater than that of the outer cover layer. The difference between the enthalpy value of the inner cushion and the enthalpy value of the outer cover layer is greater than 45 J/g.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 13, 2025
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Ying Chen Cheng, Yu Lin Chu, Cheng Yu Tsai, Hsin-Chu Lin
  • Patent number: 12245235
    Abstract: A method performed by a UE is provided. The method includes receiving at least one SL-DRX configuration and a plurality of SL resource pool configurations to be configured on the first UE; performing partial sensing based on at least one of the plurality of SL resource pool configurations when an SL-DRX operation is performed based on the at least one SL-DRX configuration, each of at least one SL resource pool configured by the at least one of the plurality of SL resource pool configurations comprising one or more time slots; and performing SL-CBR measurement associated with each of the at least one SL resource pool in the one or more time slots where the partial sensing is performed.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 4, 2025
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yung-Lan Tseng, Chia-Hao Yu, Hsin-Hsi Tsai, Yu-Hsin Cheng, Hung-Chen Chen
  • Patent number: 12232207
    Abstract: A method for a UE to perform a MUSIM operation is provided. The method includes connecting to a first network associated with a first USIM; transmitting a request message to the first network, the request message including assistance information to request a time gap for the MUSIM operation; receiving a first time gap configuration from the first network in a case that a type of the time gap requested by the UE is aperiodic, the first time gap configuration indicating a starting SFN and a starting subframe of a first configured time gap; and in a case that the UE receives the first time gap configuration, switching to a second network, while keeping a connection to the first network, during the first configured time gap according to the first time gap configuration, the second network being associated with a second USIM.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 18, 2025
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: An-An Lee, Hung-Chen Chen, Mei-Ju Shih, Yung-Lan Tseng, Hsin-Hsi Tsai
  • Patent number: 9966304
    Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an ?-phase inducing metal layer is introduced on a first Ta barrier layer of ? phase to induce the subsequent deposition of Ta thereon into the formation of an ?-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of ? phase has a lower Rc than that of the ?-phase Ta barrier layer.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung Lin, Ching-Fu Yeh, Hsin-Chen Tsai, Yao-Hsiang Liang, Yu-Min Chang, Shih-Chi Lin
  • Publication number: 20160379875
    Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an ?-phase inducing metal layer is introduced on a first Ta barrier layer of ? phase to induce the subsequent deposition of Ta thereon into the formation of an ?-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of ? phase has a lower Rc than that of the ?-phase Ta barrier layer.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung LIN, Ching-Fu YEH, Hsin-Chen TSAI, Yao-Hsiang LIANG, Yu-Min CHANG, Shih-Chi LIN
  • Publication number: 20150001720
    Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an ?-phase inducing metal layer is introduced on a first Ta barrier layer of ? phase to induce the subsequent deposition of Ta thereon into the formation of an ?-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of ? phase has a lower Rc than that of the ?-phase Ta barrier layer.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Yu-Hung Lin, Ching-Fu Yeh, Hsin-Chen Tsai, Yao-Hsiang Liang, Yu-Min Chang, Shih-Chi Lin
  • Publication number: 20050203655
    Abstract: A manufacturing equipment scheduler controls the run sequences of product lots to minimize low utilization rates of units of manufacturing equipment within a manufacturing facility. The manufacturing equipment scheduling system includes a product lot sequence controller that receives priority information of the product lots dispatched for fabrication The product lot sequence controller determines a priority of a currently dispatched product lot. If the current product lot has a high priority, the product lot sequence controller then determines if a previous product lot remains in a selected unit of processing equipment and has a normal priority. If the previous product lot has a normal priority, the product lot is removed from the selected unit of processing equipment and the product lot with the high priority is processed. Upon completion of processing the current product lot with high priority, processing for the previous product lot is continued.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Inventor: Hsin-Chen Tsai