Patents by Inventor Hsin-Cheng HSU
Hsin-Cheng HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11960201Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.Type: GrantFiled: May 15, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
-
Publication number: 20240103358Abstract: A system includes a mask. The system further includes a pellicle frame attached to the mask. The pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. The pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. The system further includes a gasket within the single recess.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN
-
Publication number: 20240094626Abstract: A pellicle for an extreme ultraviolet (EUV) photomask includes a pellicle frame and a main membrane attached to the pellicle frame. The main membrane includes a plurality of nanotubes, and each of the plurality of nanotubes is covered by a coating layer containing Si and one or more metal elements.Type: ApplicationFiled: April 12, 2023Publication date: March 21, 2024Inventors: Pei-Cheng HSU, Wei-Hao LEE, Huan-Ling LEE, Hsin-Chang LEE, Chin-Hsiang LIN
-
Publication number: 20240085781Abstract: In a method of cleaning a photo mask, the photo mask is placed on a support such that a pattered surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Hao-Ping CHENG, Ta-Cheng LIEN
-
Publication number: 20240077804Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping-Hsun LIN, Chien-Cheng CHEN, Shih Ju HUANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
-
Publication number: 20240069427Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.Type: ApplicationFiled: March 2, 2023Publication date: February 29, 2024Inventors: Ting-Pi SUN, Pei-Cheng HSU, Hsin-Chang LEE
-
Patent number: 11901892Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.Type: GrantFiled: August 16, 2022Date of Patent: February 13, 2024Assignee: MEDIATEK INC.Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
-
Patent number: 11881847Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.Type: GrantFiled: July 12, 2022Date of Patent: January 23, 2024Assignee: MEDIATEK INC.Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
-
Publication number: 20230327428Abstract: The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.Type: ApplicationFiled: March 20, 2023Publication date: October 12, 2023Applicant: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Chien-Ming Hsu, Jui-Ming Chen
-
Publication number: 20230268925Abstract: A level shifter with high reliability is shown, which has a power multiplexer receiving a plurality of power voltage candidates to selectively output a selected power voltage. In response to a low-to-high transition of the input signal of the level shifter, the first output terminal of the level shifter is pulled up to the selected power voltage by the second pull-up device, and the first pull-down device pulls down the second output terminal of the level shifter to a low-voltage level corresponding to the selected power voltage. In response to a high-to-low transition of the input signal, the second output terminal of the level shifter is pulled up to the selected power voltage by the first pull-up device, and the second pull-down device pulls down the first output terminal of the level shifter to the low-voltage level corresponding to the selected power voltage.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Hsin-Cheng HSU, Federico Agustin ALTOLAGUIRRE
-
Patent number: 11716073Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: GrantFiled: January 21, 2022Date of Patent: August 1, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Jui-Ming Chen, Federico Agustin Altolaguirre
-
Patent number: 11695395Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.Type: GrantFiled: January 19, 2022Date of Patent: July 4, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Federico Agustin Altolaguirre
-
Patent number: 11652476Abstract: The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.Type: GrantFiled: October 13, 2021Date of Patent: May 16, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Chien Wu
-
Publication number: 20230081401Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.Type: ApplicationFiled: July 12, 2022Publication date: March 16, 2023Inventors: Federico Agustin ALTOLAGUIRRE, Hsin-Cheng HSU
-
Publication number: 20230080713Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.Type: ApplicationFiled: August 16, 2022Publication date: March 16, 2023Inventors: Federico Agustin ALTOLAGUIRRE, Hsin-Cheng HSU
-
Publication number: 20220329236Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.Type: ApplicationFiled: January 19, 2022Publication date: October 13, 2022Inventors: Hsin-Cheng HSU, Federico Agustin ALTOLAGUIRRE
-
Publication number: 20220329232Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: ApplicationFiled: January 21, 2022Publication date: October 13, 2022Inventors: Hsin-Cheng HSU, Jui-Ming CHEN, Federico Agustin ALTOLAGUIRRE
-
Publication number: 20220239290Abstract: The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.Type: ApplicationFiled: October 13, 2021Publication date: July 28, 2022Applicant: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Chien Wu
-
Publication number: 20220118678Abstract: A housing structure manufacturing method and an electronic device are provided. The housing structure manufacturing method includes providing a plurality of memory polymeric materials, heating the plurality of memory polymeric materials, and forming the housing structure having a first morphology by printing the plurality of memory polymeric materials that are heated.Type: ApplicationFiled: June 25, 2019Publication date: April 21, 2022Inventors: Luca Di Fiore, SHIH-HUANG TSAI, CHIH-CHUN HUANG, HSIN-CHENG HSU
-
Patent number: 11146060Abstract: An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N?1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N?1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.Type: GrantFiled: October 11, 2018Date of Patent: October 12, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsin-Cheng Hsu, Tay-Her Tsaur, Po-Ching Lin