Patents by Inventor Hsin-cheng Lin

Hsin-cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112152
    Abstract: A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Kuan-Ying CHIU, Chee-Wee LIU
  • Patent number: 12249367
    Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chia-Che Chung, Hsin-Cheng Lin, Chee-Wee Liu
  • Publication number: 20250078917
    Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Kuan-Ying CHIU, Chee-Wee LIU
  • Publication number: 20250072100
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te TU, Hsin-Cheng LIN, Chee-Wee LIU
  • Publication number: 20250056782
    Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Tao CHOU, Hsin-Cheng LIN, Ching-Wang YAO, Li-Kai WANG, Chee-Wee LIU, Chenming HU
  • Publication number: 20250054536
    Abstract: A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Tao CHOU, Hsin-Cheng LIN, Jih-Chao CHIU, Chee-Wee LIU
  • Patent number: 12170227
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: December 17, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu
  • Publication number: 20240371933
    Abstract: Various embodiments include stacked transistors and methods of forming stacked transistors. In an embodiment, a device includes: a first nanostructure; a second nanostructure above the first nanostructure; a first gate structure extending along a top surface and a bottom surface of the first nanostructure; and a second gate structure extending along a top surface and a bottom surface of the second nanostructure. The first gate structure is disposed at a first side of the first nanostructure and a first side of the second nanostructure. The second gate structure is disposed at a second side of the first nanostructure and a second side of the second nanostructure. The second side of the first nanostructure is opposite the first side of the first nanostructure. The second side of the second nanostructure opposite the first side of the second nanostructure.
    Type: Application
    Filed: November 14, 2023
    Publication date: November 7, 2024
    Inventors: Hsin-Cheng Lin, Ching-Wang Yao, Kung-Ying Chiu, Chee Wee Liu
  • Publication number: 20240371932
    Abstract: An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 7, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Yi-Chun LIU, Kung-Ying CHIU, Chee-Wee LIU
  • Publication number: 20240363624
    Abstract: A device includes a semiconductor substrate, a first transistor, a second transistor over the first transistor and a first isolation structure. The first transistor is on the semiconductor substrate. The first transistor comprises a first channel, a first source and a first drain. The first source and the first drain are on opposite sides of the first channel. The second transistor comprises a second channel, a second source and a second drain. The second source and the second drain are on opposite sides of the second channel. The first transistor is connected in series with the second transistor. The first isolation structure is vertically between the first drain and the second source.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Ching-Wang YAO, Kung-Ying CHIU, Chee-Wee LIU
  • Publication number: 20240347536
    Abstract: An integrated circuit includes a first transistor and a second transistor. The first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. The second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. The first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. A thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Chun-Yi CHENG, Ching-Wang YAO, Chee-Wee LIU
  • Publication number: 20240339530
    Abstract: An integrated circuit includes a first transistor and a second transistor. The first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. The second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. The first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. A thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Chun-Yi CHENG, Ching-Wang YAO, Chee-Wee LIU
  • Publication number: 20240284653
    Abstract: A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • Publication number: 20240243165
    Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • Publication number: 20240204065
    Abstract: A high frequency transistor includes a substrate, a plurality of gates, a plurality of sources/drains, a first metal layer, a plurality of source/drain contacts, and a plurality of first gate contacts. The gates extend along a first direction on a surface of the substrate, and the sources/drains are disposed in the substrate on both sides of each of the gates. The first metal layer has a first portion extending along the first direction and a second portion extending along a second direction, and the first direction is perpendicular to the second direction. The first portion is a discontinuous line segment having a discontinuous region in the second direction, and the second portion is a continuous line segment passing through the discontinuous region. The source/drain contacts are respectively connected to the first portion and the sources/drains. The first gate contacts are respectively connected to the second portion and the gates.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 20, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsin-Cheng Lin, Avishek Das, Kuan-Ying Chiu, Chee-Wee Liu
  • Patent number: 11955384
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: April 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu
  • Patent number: 11880747
    Abstract: An image recognition method, a training system for an object recognition model and a training method for an object recognition model are provided. The image recognition method includes the following steps. At least one original sample image of an object in a field and an object range information and an object type information in the original sample image are obtained. At least one physical parameter is adjusted to generate plural simulated sample images of the object. The object range information and the object type information of the object in each of the simulated sample images are automatically marked. A machine learning procedure is performed to train an object recognition model. An image recognition procedure is performed on an input image.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 23, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Cheng Lin, Sen-Yih Chou
  • Publication number: 20240021479
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te TU, Hsin-Cheng LIN, Chee-Wee LIU
  • Publication number: 20230395648
    Abstract: The method includes forming a sacrificial multi-layer stack including alternating first sacrificial layers and second sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layers to form first spaces each interposing two of the second sacrificial layers; depositing a first dielectric layer and a first electrode material in the first spaces; removing the second sacrificial layers to form second spaces each interposing two portions of the first electrode material; depositing a second dielectric layer and a second electrode material in the second spaces.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Chia-Che CHUNG, Chee-Wee LIU
  • Patent number: 11823438
    Abstract: A recognition system and an image augmentation and training method thereof are provided. The image augmentation and training method of a recognition system includes the following steps. A plurality of image frames are obtained, wherein each of the image frames includes an object pattern. A plurality of environmental patterns are obtained. The object pattern is separated from each of the image frames. A plurality of image parameters are set. The image frames, based on the object patterns and the environmental patterns, are augmented according to the image parameters to increase the number of the image frames. A recognition model is trained using the image frames.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 21, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Hsun Cheng, Yu-Ju Chao, Hsin-Cheng Lin, Chih-Chia Chang, Yu-Hsin Lin, Sen-Yih Chou