Abstract: A touch panel circuit and an operation method thereof are disclosed herein. The touch panel circuit includes first scan lines, second scan lines, and a first scan sensing module. The first scan sensing module includes first scan-sensing units corresponding to the first scan lines, respectively. Each first scan sensing unit includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a first output terminal, and a first control terminal. The second logic gate includes a second input terminal, a second output terminal, and a second control terminal. The first logic gate and second logic gate enable the first input terminal to connect to the first output terminal and one of the first scan lines, or enable the second input terminal and one of the first scan lines to connect to the second output terminal.

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract: A touch panel circuit and an operation method thereof are disclosed herein. The touch panel circuit includes first scan lines, second scan lines, and a first scan sensing module. The first scan sensing module includes first scan-sensing units corresponding to the first scan lines, respectively. Each first scan sensing unit includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a first output terminal, and a first control terminal. The second logic gate includes a second input terminal, a second output terminal, and a second control terminal. The first logic gate and second logic gate enable the first input terminal to connect to the first output terminal and one of the first scan lines, or enable the second input terminal and one of the first scan lines to connect to the second output terminal.

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract: A voltage-controlled oscillator (VCO) is provided. The VCO includes an oscillator unit disposed on a substrate, and a varactor unit. The varactor unit is coupled to the oscillator unit to form a VCO loop. The varactor unit includes a varactor and at least one control terminal. The varactor is disposed in the substrate, and includes at least two through-silicon via (TSV) structures. The at least one control terminal renders the varactor unit to be biased to change a capacitance value of the varactor.

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract: A computer apparatus is provided, which includes a function key, controller, basic input/output system (BIOS) unit and operating system (OS) unit. The function key is used for activating a predetermined function of the computer apparatus and outputting a control signal when the function key is enabled. The controller is used for receiving the control signal and sending a corresponding function code and a scan code. The BIOS unit is used for receiving and storing the function code. The OS unit has an application program. The OS unit receives the scan code, receives the function code based on the scan code and executes a corresponding process based on the function code.