Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: An electronic test equipment is adapted to test an electronic component. The electronic component has a circuit body and a plurality of connectors that are electrically connected to the circuit body. The electronic test equipment includes a metallic test seat and a plurality of spring probes. The metallic test seat is adapted to support the circuit body thereon, and is formed with a plurality of spaced-apart probe holes extending therethrough and possessing diameters that are substantially the same. Each of the probe holes is adapted to receive a corresponding one of the connectors. The spring probes are respectively and entirely positioned within the probe holes, and are adapted to electrically contact the connectors.

Abstract: A wafer probe card has an adapter module and a probe module detachably mounted together. The adapter module has a holding member and an interposer mounted within the holding plate. The probe module has a frame assembly and a space transformer and a probe assembly mounted within the frame assembly. A fixing plate is mounted on the holding member of the adapter module to constitute an electrical connection among the interposer, space transformer and probe assembly. When any element of the wafer probe card is faulty, the adapter module or the probe module is detached and the faulty element is replaced. The adapter module or the probe module with the replaced element is then reassembled. Alternatively, the adapter module or the probe module can be replaced on a modular basis. Accordingly, it is not necessary that all components be detached entirely, thereby improving the operational speed and efficiency.

Abstract: A wafer probe card has an adapter module and a probe module detachably mounted together. The adapter module has a holding member and an interposer mounted within the holding plate. The probe module has a frame assembly and a space transformer and a probe assembly mounted within the frame assembly. A fixing plate is mounted on the holding member of the adapter module to constitute an electrical connection among the interposer, space transformer and probe assembly. When any element of the wafer probe card is faulty, the adapter module or the probe module is detached and the faulty element is replaced. The adapter module or the probe module with the replaced element is then reassembled. Alternatively, the adapter module or the probe module can be replaced on a modular basis. Accordingly, all components are unnecessarily to be detached entirely, thereby improving the operational speed and efficiency.

Abstract: A chip package structure with a shielding cover includes a substrate, a chip, a pair of first passive components, a pair of second passive components, and a shielding cover. The chip, the pair of first passive components, the pair of second passive components, and the shielding cover are disposed on the substrate. The chip is electrically connected to the substrate. The shielding cover covers the chip and has leads connected to the substrate. The leads include a first lead and a second lead. The first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components. The second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.

Abstract: A tool and a method for packaging lens module are provided. The method for packaging lens module includes the following steps. Firstly, a carrier having at least one cavity is provided. Next, a holder is disposed in the cavity. Then, a die is disposed on a surface of a substrate. After that, the substrate is inversely placed on the carrier, wherein the surface where the die is disposed faces the carrier, and the die corresponds to the holder. Then, a cover plate covers the carrier and the substrate, such that the substrate is fixed on the holder.

Abstract: A chip package structure with a shielding cover includes a substrate, a chip, a pair of first passive components, a pair of second passive components, and a shielding cover. The chip, the pair of first passive components, the pair of second passive components, and the shielding cover are disposed on the substrate. The chip is electrically connected to the substrate. The shielding cover covers the chip and has leads connected to the substrate. The leads include a first lead and a second lead. The first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components. The second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.

Abstract: A tool and a method for packaging lens module are provided. The method for packaging lens module includes the following steps. Firstly, a carrier having at least one cavity is provided. Next, a holder is disposed in the cavity. Then, a die is disposed on a surface of a substrate. After that, the substrate is inversely placed on the carrier, wherein the surface where the die is disposed faces the carrier, and the die corresponds to the holder. Then, a cover plate covers the carrier and the substrate, such that the substrate is fixed on the holder.

Abstract: An image-capturing module and a manufacturing method thereof are provided. The image-capturing module includes a circuit board, an electric element, a lens set and a carrier. The circuit board has at least a locking hole. The electric element is disposed on the circuit board. The carrier is disposed on the circuit board for carrying the lens set. The carrier has at least a hook locking at the locking hole of the circuit board.

Abstract: A package structure is provided. The package structure includes a substrate, a semiconductor device, and a shielding cap. The substrate has at least an alignment recess located at a corner of the substrate. The semiconductor device is disposed on an upper surface of the substrate. The shielding cap having an alignment pin covers the semiconductor device. The alignment pin is inserted into the alignment recess.

Abstract: A strip test method includes the following steps. First, an assembly strip is provided, wherein the assembly strip includes a plurality of semiconductor devices, each having a plurality of leads. A test socket and a base are provided, wherein the test socket has a plurality of probe sets. The assembly strip is loaded to the base. The probe sets electrically contacts the leads of the semiconductor devices simultaneously and respectively so as to process an electrical test. When one of the semiconductor devices is failed in the electrical test, one of the base and the test socket are relatively moved in such a manner that the failed one of the semiconductor devices is corresponding to one of the probe sets which is successful in the electrical test and is the nearest to the failed one of semiconductor device. Finally, the successful and nearest one of probe sets simultaneously and electrically contacts the leads of the failed one of the semiconductor devices so as to process another electrical test again.

Abstract: A strip test method includes the following steps. First, an assembly strip is provided, wherein the assembly strip includes a plurality of semiconductor devices, each having a plurality of leads. A test socket and a base are provided, wherein the test socket has a plurality of probe sets. The assembly strip is loaded to the base. The probe sets electrically contacts the leads of the semiconductor devices simultaneously and respectively so as to process an electrical test. When one of the semiconductor devices is failed in the electrical test, one of the base and the test socket are relatively moved in such a manner that the failed one of the semiconductor devices is corresponding to one of the probe sets which is successful in the electrical test and is the nearest to the failed one of semiconductor device. Finally, the successful and nearest one of probe sets simultaneously and electrically contacts the leads of the failed one of the semiconductor devices so as to process another electrical test again.