Patents by Inventor Hsin-Chih Yu
Hsin-Chih Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197153Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: ApplicationFiled: January 20, 2022Publication date: June 22, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Patent number: 11475953Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.Type: GrantFiled: July 16, 2021Date of Patent: October 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang
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Patent number: 10978122Abstract: A memory includes (n?1) non-volatile cells, (n?1) bit lines and a current driving circuit. Each of the (n?1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n?1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n?1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n?1) non-volatile cells.Type: GrantFiled: February 21, 2020Date of Patent: April 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Ya-Lan Chiou, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
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Publication number: 20200395073Abstract: A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.Type: ApplicationFiled: July 4, 2019Publication date: December 17, 2020Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Shu-Ru Wang
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Patent number: 10861549Abstract: A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.Type: GrantFiled: July 4, 2019Date of Patent: December 8, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Shu-Ru Wang
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Patent number: 10706914Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.Type: GrantFiled: June 26, 2018Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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Publication number: 20190362776Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.Type: ApplicationFiled: June 26, 2018Publication date: November 28, 2019Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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Memory device with oxide semiconductor static random access memory and method for operating the same
Patent number: 10410684Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.Type: GrantFiled: February 21, 2018Date of Patent: September 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu -
Patent number: 10366756Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.Type: GrantFiled: August 19, 2018Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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MEMORY DEVICE WITH OXIDE SEMICONDUCTOR STATIC RANDOM ACCESS MEMORY AND METHOD FOR OPERATING THE SAME
Publication number: 20190221238Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.Type: ApplicationFiled: February 21, 2018Publication date: July 18, 2019Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu -
Patent number: 9193603Abstract: The present invention relates to an urchin-like iron oxide and a method for producing the urchin-like iron oxide. The urchin-like iron oxide comprises a core and multiple needle-like elongations protruded from the core. The needle-like elongations could be wire, rod, tube, cone, and flake. The length/width ratio of the needle-like elongation is high enough to apply in an optoelectronic field. The method in accordance with the present invention is to stably heat an iron-contained powder under room temperature by a thermal oxidation. The surface of the iron-contained powder is slow oxidized to form an urchin-like iron oxide with multiple uniform distributed needle-like elongations protruded from the surface. The size of each needle-like elongation is easily adjusted and changed by controlling the heating temperature. The method has advantages of simplified operation and lowered expense.Type: GrantFiled: December 12, 2012Date of Patent: November 24, 2015Assignee: NATIONAL CHUNG CHENG UNIVERSITYInventors: Yuan-Yao Li, Hsin-Chih Yu, Li-Chieh Hsu
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Patent number: 8486790Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.Type: GrantFiled: July 18, 2011Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
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Publication number: 20130023098Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
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Publication number: 20120114944Abstract: The present invention relates to an urchin-like iron oxide and a method for producing the urchin-like iron oxide. The urchin-like iron oxide comprises a core and multiple needle-like elongations protruded from the core. The needle-like elongations could be wire, rod, tube, cone, and flake. The length/width ratio of the needle-like elongation is high enough to apply in an optoelectronic field. The method in accordance with the present invention is to stably heat an iron-contained powder under room temperature by a thermal oxidation. The surface of the iron-contained powder is slow oxidized to form an urchin-like iron oxide with multiple uniform distributed needle-like elongations protruded from the surface. The size of each needle-like elongation is easily adjusted and changed by controlling the heating temperature. The method has advantages of simplified operation and lowered expense.Type: ApplicationFiled: April 4, 2011Publication date: May 10, 2012Inventors: Yuan-Yao LI, Hsin-Chih Yu, Li-Chieh Hsu