Patents by Inventor Hsin-Chin Chang
Hsin-Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134107Abstract: A light source device includes a light guide plate, an optical adhesive, and a light source element. The light guide plate includes a light guide substrate and an enhancement layer. The light guide substrate has a light incident surface, a first surface, and a second surface. The first surface is opposite to the second surface, and the light incident surface extends between the first surface and the second surface. The enhancement layer is disposed on the light guide substrate. A thickness of the enhancement layer is from 1 micrometer to 25 micrometers and a first refractive index of the light guide substrate is greater than a second refractive index of the enhancement layer. The optical adhesive is interposed between the first surface of the light guide substrate and the optical adhesive. The light source element is disposed beside the light incident surface to emit light toward the light incident surface.Type: ApplicationFiled: June 26, 2023Publication date: April 25, 2024Applicant: E Ink Holdings Inc.Inventors: Hsin-Tao Huang, Yu-Chuan Wen, Jen-Pin Yu, Ching-Huan Liao, Ya-Chin Chang
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Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
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Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
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Patent number: 9332646Abstract: An electronic package module includes a circuit board having a supporting surface, at least one first electronic component, at least one second electronic component, and at least one molding compound. The first and second electronic components are mounted on the supporting surface. The molding compound is disposed on the supporting surface and covers the supporting surface partially. The molding compound encapsulates the first electronic component yet not the second electronic component.Type: GrantFiled: January 19, 2013Date of Patent: May 3, 2016Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.Inventors: Jen-Chun Chen, Hsin-Chin Chang
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Patent number: 9167686Abstract: A 3D stacked package structure includes a first unit, a molding unit, a conductive unit and a second unit. The first unit includes a first substrate and at least one first electronic component, and the first substrate has at least one runner and at least one first conductive pad. The molding unit includes a top portion, a frame, and at least one connection connected between the top portion and the frame. The conductive unit includes at least one conductor passing through the frame and electrically connected to the first conductive pad. Therefore, the first unit can be stacked on the second unit through the frame of the molding unit, and the first unit can be electrically connected to the second unit through the conductor of the conductive unit.Type: GrantFiled: March 1, 2013Date of Patent: October 20, 2015Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.Inventors: Jenchun Chen, Hsin Chin Chang
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Patent number: 9141125Abstract: A bandgap reference voltage generating circuit for providing a reference voltage is disclosed. The bandgap reference voltage generating circuit includes four-terminal current source circuit, a regulator circuit and a temperature-compensating circuit. The four-terminal current source circuit outputs a first voltage, a second voltage and a first current which are independent of variation of a first system voltage. The regulator circuit receives the first voltage and the second voltage and when the first system voltage is larger than a threshold voltage value, the regulator circuit outputs the reference voltage independent of variation of the first system voltage via voltage-difference between the first voltage and the second voltage. The temperature-compensating circuit receives the first current and compensates a temperature curve of the reference voltage outputted from the regulator circuit.Type: GrantFiled: September 3, 2013Date of Patent: September 22, 2015Assignee: Advanced Semiconductor Engineering Inc.Inventors: Jaw-Ming Ding, Hsin-Chin Chang
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Patent number: 9089046Abstract: An electronic module includes a circuit board, a plurality of electronic components, a plurality of molding layers, at least one first conductive layer, at least one insulating filler, and one second conductive layer. The circuit board has a first plane and at least one grounding pad on the first plane. The electronic components are mounted on the first plane and electrically connected with the circuit board. The molding layers cover the electronic components and the first plane. The trench appears between two adjacent molding layers. The grounding pad is positioned at the bottom of the trench. The first conductive layer covers the sidewall of the trench and the grounding pad. The grounding pad electrically connected with the first conductive layer. The insulating filler is positioned in the trench. The second conductive layer covers the molding layers and the insulating filler, and electrically connects with the first conductive layer.Type: GrantFiled: January 23, 2013Date of Patent: July 21, 2015Assignees: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD., UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD.Inventors: Jen-Chun Chen, Pai-Sheng Shih, Hsin-Chin Chang
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Patent number: 9065389Abstract: A radio frequency (RF) power amplifier with no reference voltage for biasing is disclosed. The RF power amplifier includes a three-terminal current source circuit, a current mirror circuit and an output-stage circuit. The three-terminal current source circuit receives a first system voltage and accordingly outputs a first current and a second current, and a source voltage exists between a first output terminal of the first current and a second output terminal of the second current. The current mirror circuit receives the first current and the second current and accordingly generates a bias current. The output-stage circuit receives the bias current so as to work at an operation point.Type: GrantFiled: August 26, 2013Date of Patent: June 23, 2015Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Jaw-Ming Ding, Hsin Chin Chang
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Patent number: 9013238Abstract: A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage.Type: GrantFiled: September 3, 2013Date of Patent: April 21, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jaw-Ming Ding, Jia-Hong Mou, Hsin-Chin Chang
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Publication number: 20140368277Abstract: A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage.Type: ApplicationFiled: September 3, 2013Publication date: December 18, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: JAW-MING DING, JIA-HONG MOU, HSIN-CHIN CHANG
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Publication number: 20140354259Abstract: A bandgap reference voltage generating circuit for providing a reference voltage is disclosed. The bandgap reference voltage generating circuit includes four-terminal current source circuit, a regulator circuit and a temperature-compensating circuit. The four-terminal current source circuit outputs a first voltage, a second voltage and a first current which are independent of variation of a first system voltage. The regulator circuit receives the first voltage and the second voltage and when the first system voltage is larger than a threshold voltage value, the regulator circuit outputs the reference voltage independent of variation of the first system voltage via voltage-difference between the first voltage and the second voltage. The temperature-compensating circuit receives the first current and compensates a temperature curve of the reference voltage outputted from the regulator circuit.Type: ApplicationFiled: September 3, 2013Publication date: December 4, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: JAW-MING DING, HSIN-CHIN CHANG
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Publication number: 20140327482Abstract: A radio frequency (RF) power amplifier with no reference voltage for biasing is disclosed. The RF power amplifier includes a three-terminal current source circuit, a current mirror circuit and an output-stage circuit. The three-terminal current source circuit receives a first system voltage and accordingly outputs a first current and a second current, and a source voltage exists between a first output terminal of the first current and a second output terminal of the second current. The current mirror circuit receives the first current and the second current and accordingly generates a bias current. The output-stage circuit receives the bias current so as to work at an operation point.Type: ApplicationFiled: August 26, 2013Publication date: November 6, 2014Applicant: ADVANCED SIMICONDUCTOR ENGINEERING INC.Inventors: JAW-MING DING, HSIN CHIN CHANG
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Patent number: 8742573Abstract: A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein at least one of the first electronic components has a first conductive contact. The second electronic component is disposed in the second region. The first covering layer includes a recess and a first exposing region for exposing the first conductive contact. The wiring layer is formed on the recess and electronically coupled to the first conductive contact.Type: GrantFiled: January 17, 2013Date of Patent: June 3, 2014Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.Inventors: Jenchun Chen, Hsin Chin Chang
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Publication number: 20140126161Abstract: An electronic package module includes a circuit board having a supporting surface, at least one first electronic component, at least one second electronic component, and at least one molding compound. The first and second electronic components are mounted on the supporting surface. The molding compound is disposed on the supporting surface and covers the supporting surface partially. The molding compound encapsulates the first electronic component yet not the second electronic component.Type: ApplicationFiled: January 19, 2013Publication date: May 8, 2014Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: JEN-CHUN CHEN, HSIN-CHIN CHANG
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Publication number: 20140104799Abstract: A 3D stacked package structure includes a first unit, a molding unit, a conductive unit and a second unit. The first unit includes a first substrate and at least one first electronic component, and the first substrate has at least one runner and at least one first conductive pad. The molding unit includes a top portion, a frame, and at least one connection connected between the top portion and the frame. The conductive unit includes at least one conductor passing through the frame and electrically connected to the first conductive pad. Therefore, the first unit can be stacked on the second unit through the frame of the molding unit, and the first unit can be electrically connected to the second unit through the conductor of the conductive unit.Type: ApplicationFiled: March 1, 2013Publication date: April 17, 2014Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: JENCHUN CHEN, HSIN CHIN CHANG
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Publication number: 20140084483Abstract: A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein at least one of the first electronic components has a first conductive contact. The second electronic component is disposed in the second region. The first covering layer includes a recess and a first exposing region for exposing the first conductive contact. The wiring layer is formed on the recess and electronically coupled to the first conductive contact.Type: ApplicationFiled: January 17, 2013Publication date: March 27, 2014Applicants: Universal Global Scientific Industrial Co., Ltd., Universal Scientific Industrial (Shanghai) Co., Ltd.Inventors: JENCHUN CHEN, HSIN CHIN CHANG
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Patent number: 7127228Abstract: A portable electronic device with power failure recovery, powered by a main power source, the device comprising a power detection module, a processor, a timing unit and a power management unit. The power detection module detects an output characteristic from the main power source and asserts an interrupt signal if the characteristic is below a threshold value. The processor asserts a turn-off signal and an enable signal in response to the interrupt signal. The timing unit asserts a notification signal at a predetermined time interval when the enable signal is asserted. Upon receipt of the turn-off signal, the power management unit disconnects the main power source from a circuit block. Moreover, the power management unit reconnects the main power source to the circuit block when the notification signal is asserted and the output characteristic of the main power source is beyond the threshold value.Type: GrantFiled: December 7, 2001Date of Patent: October 24, 2006Assignee: Acer Communications and Multimedia Inc.Inventors: Hsin-Chin Chang, Chen-Huang Fan, Ben-Chuan Du
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Publication number: 20030109243Abstract: A portable electronic device with power failure recovery, powered by a main power source, the device comprising a power detection module, a processor, a timing unit and a power management unit. The power detection module detects an output characteristic from the main power source and asserts an interrupt signal if the characteristic is below a threshold value. The processor asserts a turn-off signal and an enable signal in response to the interrupt signal. The timing unit asserts a notification signal at a predetermined time interval when the enable signal is asserted. Upon receipt of the turn-off signal, the power management unit disconnects the main power source to a circuit block with high power consumption. Moreover, the power management unit reconnects the main power source to the circuit block when the notification signal is asserted and the output characteristic of the main power source is beyond the threshold value.Type: ApplicationFiled: December 7, 2001Publication date: June 12, 2003Applicant: Acer Communications and Multimedia Inc.Inventors: Hsin-Chin Chang, Chen-Huang Fan, Ben-Chuan Du