Patents by Inventor Hsin-Chou Liu

Hsin-Chou Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11517231
    Abstract: A blood glucose test strip includes a base substrate, a calibration site, a test site and a non-volatile memory. The calibration site is disposed on the base substrate. A chemical reagent is applied on the calibration site. The test site is disposed on the base substrate. A chemical reagent is applied on the test site. The non-volatile memory is disposed on the base substrate. A calibration parameter is stored in the non-volatile memory. During a calibrating procedure, the calibration solution is dropped on the calibration site, a calibration parameter is calculated according to a first reaction result of the calibration solution and the chemical reagent, and the calibration parameter is stored in the non-volatile memory.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 6, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Hsin-Chou Liu
  • Patent number: 11030346
    Abstract: An integrated circuit includes a core circuit and a function lock circuit. The core circuit includes at least one function block circuit. The function lock circuit is coupled to the core circuit. The function lock circuit includes a random number source, an entanglement circuit, and a memory. The random number source is configured to generate a random code. The entanglement circuit is coupled to the random number source and the core circuit and configured to generate an unlocking code according to the random code and a command signal. The memory is coupled to the entanglement circuit and configured to store the unlocking code. The at least one function block circuit of the core circuit is determined to be locked/unlocked according to a presence of the unlocking code.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 8, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Hsin-Chou Liu
  • Publication number: 20200221987
    Abstract: A blood glucose test strip includes a base substrate, a calibration site, a test site and a non-volatile memory. The calibration site is disposed on the base substrate. A chemical reagent is applied on the calibration site. The test site is disposed on the base substrate. A chemical reagent is applied on the test site. The non-volatile memory is disposed on the base substrate. A calibration parameter is stored in the non-volatile memory. During a calibrating procedure, the calibration solution is dropped on the calibration site, a calibration parameter is calculated according to a first reaction result of the calibration solution and the chemical reagent, and the calibration parameter is stored in the non-volatile memory.
    Type: Application
    Filed: December 10, 2019
    Publication date: July 16, 2020
    Inventor: Hsin-Chou LIU
  • Publication number: 20200021437
    Abstract: An integrated circuit includes a core circuit and a function lock circuit. The core circuit includes at least one function block circuit. The function lock circuit is coupled to the core circuit. The function lock circuit includes a random number source, an entanglement circuit, and a memory. The random number source is configured to generate a random code. The entanglement circuit is coupled to the random number source and the core circuit and configured to generate an unlocking code according to the random code and a command signal. The memory is coupled to the entanglement circuit and configured to store the unlocking code. The at least one function block circuit of the core circuit is determined to be locked/unlocked according to a presence of the unlocking code.
    Type: Application
    Filed: May 28, 2019
    Publication date: January 16, 2020
    Inventor: Hsin-Chou Liu
  • Patent number: 9638549
    Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 2, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ren Chen, Wen-Hao Lee, Hsin-Chou Liu, Ching-Sung Yang
  • Publication number: 20160197899
    Abstract: A dynamic encryption type fingerprint sensor includes a capacitive array sensing fingerprints and producing fingerprint data, an embedded non-volatile memory (eNVM) storing a one-time code (OTC) and an encryption algorithm indicator, and a logic algorithm circuit encrypting the fingerprint data produced by the capacitive array according to the OTC and the encryption algorithm indicator. The logic algorithm circuit includes an encryption circuit having a plurality of logic encryption circuits selected using the encryption algorithm indicator, the encryption circuit encrypting the fingerprint data using selected logic encryption circuits of the plurality of logic encryption circuits according to the OTC. A control circuit is used for controlling operation of the capacitive array, the eNVM, and the logic algorithm circuit.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 7, 2016
    Inventors: Hsin-Chou Liu, Hung-Hsiang Wang
  • Publication number: 20160123775
    Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.
    Type: Application
    Filed: June 3, 2015
    Publication date: May 5, 2016
    Inventors: Wei-Ren Chen, Wen-Hao Lee, Hsin-Chou Liu, Ching-Sung Yang