Abstract: A multi-computer vision recognition system for a level crossing obstacle is disclosed, comprising vision image systems, a position determination system, an obstacle determination resolution system and a power unit, where vision image systems which may operate all day long operate simultaneously, information of the single vision image systems is each computed by using the position determination system, and then the computed result is introduced to the obstacle determination resolution system for determination, whereby achieving an increased obstacle recognition result and a promoted obstacle recognition accuracy.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

Abstract: A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.

Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.