Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: A method for manufacturing a working electrode of electrochemical sensor comprises the steps of: step S1, providing a substrate; step S2, forming a wavy pattern on the substrate; and step S3, disposing a conductive substance on the wavy pattern. A working electrode of electrochemical sensor is also disclosed.

Abstract: A method for manufacturing a working electrode of electrochemical sensor comprises the steps of: providing a substrate; forming a defined pattern on the substrate; and disposing a plurality of conductive particles on the defined pattern.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which are respectively corresponded to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: A method for forming a bottle-shaped trench. A conductive layer surrounded by a doped layer is filled in a lower portion of a trench formed in a substrate. A doping region is formed in the substrate around the doped layer by a heat treatment. A collar silicon nitride layer is formed over an upper portion of the sidewall of the trench. The conductive layer and the doped layer are successively removed using the collar silicon nitride layer as a mask. The doping region is partially oxidized to form a doped oxide region thereon. The doped oxide region is removed to form a bottle-shaped trench. A conformable rugged polysilicon layer is formed in the lower portion of the bottle-shaped trench.

Abstract: A humidity sensor and fabrication method thereof. In the humidity sensor of the present invention, two comb-type electrodes with a plurality of teeth are disposed on a semiconductor substrate. A SiO2 sensing film is disposed between the teeth of the two comb-type electrodes on the substrate. A predetermined voltage is applied between the two comb-type electrodes, a leakage current between the two electrodes is detected, and the humidity in the environment is measured according thereto.

Abstract: A method for fabricating a bottle-shaped trench capacitor. A first conductive layer surrounded by a doped layer is filled in the lower portion of a trench in a substrate. A buried bottom plate is formed in the substrate near the doped layer by a heat treatment. A collar insulating layer is formed over the sidewall of the upper portion of the trench. The first conductive layer and the doped layer are removed using the collar insulating layer as a mask, and then a portion of the doping region is etched to form a bottle-shaped trench. A rugged polysilicon layer and a capacitor dielectric layer are conformably formed in the lower portion of the trench which is subsequently filled with a second conductive layer to serve as a top plate.

Abstract: A method for forming a bottle-shaped trench. A conductive layer surrounded by a doped layer is filled in a lower portion of a trench formed in a substrate. A doping region is formed in the substrate around the doped layer by a heat treatment. A collar silicon nitride layer is formed over an upper portion of the sidewall of the trench. The conductive layer and the doped layer are successively removed using the collar silicon nitride layer as a mask. The doping region is partially oxidized to form a doped oxide region thereon. The doped oxide region is removed to form a bottle-shaped trench. A conformable rugged polysilicon layer is formed in the lower portion of the bottle-shaped trench.

Abstract: A chemical mechanical polish apparatus comprises a platen having a polishing pad thereon, a wafer carrier holding a wafer on the polishing pad, and a pusher. The pusher has a base disk and at least two guiding structures at the rim of the base disk. Each guiding structure has a shell with an opening, an elastic device and a pin moving through the opening, wherein the opening is non-linear.

Abstract: A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Abstract: A humidity sensor and fabrication method thereof. In the humidity sensor of the present invention, two comb-type electrodes with a plurality of teeth are disposed on a semiconductor substrate. A SiO2 sensing film is disposed between the teeth of the two comb-type electrodes on the substrate. A predetermined voltage is applied between the two comb-type electrodes, a leakage current between the two electrodes is detected, and the humidity in the environment is measured according thereto.

Abstract: A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Abstract: A chemical mechanical polish apparatus comprises a platen having a polishing pad thereon, a wafer carrier holding a wafer on the polishing pad, and a pusher. The pusher has a base disk and at least two guiding structures at the rim of the base disk. Each guiding structure has a shell with an opening, an elastic device and a pin moving through the opening, wherein the opening is non-linear.

Abstract: A method for forming shallow trench isolation in an integrated circuit is introduced. Firstly, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. Then lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is performed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spin-on-glass. Then curing at temperature above 800° C. and etching back are performed with silicon nitride as end point.

Abstract: A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron.

Abstract: This invention relates to a dual damascene process with porous low-k dielectric material. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.

Abstract: The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention.