Patents by Inventor Hsin-Fen Li

Hsin-Fen Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Localized spacer for nanowire transistors and methods of fabrication
    Patent number: 12176408
    Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Sudipto Naskar, Willy Rachmady, Hsin-Fen Li, Christopher Parker, Prashant Wadhwa, Tahir Ghani, Mohammad Hasan, Jianqiang Lin
  • LOCALIZED SPACER FOR NANOWIRE TRANSISTORS AND METHODS OF FABRICATION
    Publication number: 20220199797
    Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Sudipto Naskar, Willy Rachmady, Hsin-Fen Li, Christopher Parker, Prashant Wadhwa, Tahir Ghani, Mohammad Hasan, Jianqiang Lin