Patents by Inventor Hsin-Fu Huang

Hsin-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265255
    Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.
    Type: Application
    Filed: September 30, 2020
    Publication date: August 26, 2021
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Publication number: 20210057643
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: September 20, 2019
    Publication date: February 25, 2021
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200266199
    Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Patent number: 10685964
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20200168450
    Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Kuan-Hsiang Chen, Hsin-Fu Huang, Chun-Ling Lin, Sheng-Yi Su, Pei-Hsun Kao
  • Patent number: 10497617
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Publication number: 20190229014
    Abstract: A method for fabricating a semiconductor structure is disclosed. A bit line is formed on a substrate. The bit line comprises a tungsten layer and cap layer on the tungsten layer. A low-temperature physical vapor deposition (PVD) process is performed to deposit a silicon nitride spacer layer covering the bit line and the substrate. The silicon nitride spacer layer is in direct contact with the tungsten layer. The low-temperature PVD process is performed at a temperature ranging between 200˜400° C.
    Type: Application
    Filed: February 4, 2018
    Publication date: July 25, 2019
    Inventors: Kuan-Chun Lin, Hsin-Fu Huang, Wei-Chih Chen
  • Publication number: 20190122925
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10199228
    Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
  • Patent number: 10199269
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Publication number: 20180337187
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 22, 2018
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20180301458
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: March 15, 2018
    Publication date: October 18, 2018
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10068797
    Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 10043811
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 7, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20180151428
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 9985110
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 29, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Publication number: 20170323950
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9755047
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 5, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu