Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure. The opening overlies at least a portion of the semiconductor device.

Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

Abstract: A field effect transistor includes a source-side doped well, a drift-region well, a source region, a drain region; a shallow trench isolation structure including a first portion overlying the drift-region well and laterally spaced from the source-side doped well; a gate dielectric layer; a gate electrode overlying the gate dielectric layer; and a proximal doped layer stack embedded within the drift-region well and interposed between the source-side doped well and the first portion of the shallow trench isolation structure. Proximal doped semiconductor layers of the proximal doped layer stack have different average atomic concentrations of dopants of the second conductivity type.

Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).