Patents by Inventor Hsin-Fu Huang

Hsin-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529697
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10515899
    Abstract: A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching-Fu Chang
  • Patent number: 10497617
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10464808
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Publication number: 20190296186
    Abstract: The present disclosure provides a light-emitting device comprises a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first light-emitting layer separated from the topmost surface by a first distance; a second semiconductor stack arranged on the substrate, and comprising a second light-emitting layer separated from the topmost surface by a second distance; and a third semiconductor stack arranged on the substrate, and comprising third light-emitting layer separated from the topmost surface by a third distance; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights; and wherein the second distance is different form the first distance and the third distance.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
  • Publication number: 20190267274
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10392244
    Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to some embodiments of the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Hung, Shao-Chi Yu, Hsiang-Fu Chen, Wen-Chuan Tai, Hsin-Ting Huang
  • Publication number: 20190252323
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20190244787
    Abstract: A plasma etching reaction chamber includes a casing having a receiving chamber; a base liftably installed below the receiving chamber; a first electrode and a second electrode; and a radio frequency electrode rod. The second electrode has a plurality of water channels and a bottom of the second electrode is installed with two cooling water tubes which are communicated with the plurality of water channels; upper sides of the two cooling water tubes are hidden within the driving rod and lower sides thereof extend downwards to be out of the casing so that external cooling water can flow into the cooling water tubes and then to the water channels to achieve the object of cooling.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 8, 2019
    Inventors: Wei-Chuan Chou, Zhi Kai Huang, Mu-Chun Ho, Chun-Fu Wang, Yi-Hsiang Chen, Hsin-Chih Chiu, Yao-Syuan Cheng
  • Publication number: 20190229014
    Abstract: A method for fabricating a semiconductor structure is disclosed. A bit line is formed on a substrate. The bit line comprises a tungsten layer and cap layer on the tungsten layer. A low-temperature physical vapor deposition (PVD) process is performed to deposit a silicon nitride spacer layer covering the bit line and the substrate. The silicon nitride spacer layer is in direct contact with the tungsten layer. The low-temperature PVD process is performed at a temperature ranging between 200˜400° C.
    Type: Application
    Filed: February 4, 2018
    Publication date: July 25, 2019
    Inventors: Kuan-Chun Lin, Hsin-Fu Huang, Wei-Chih Chen
  • Publication number: 20190229233
    Abstract: A light-emitting device is provided. The light-emitting device comprises a substrate; an insulating layer on the substrate, wherein the insulating layer comprises a first hole; a light-emitting stack on the insulating layer and comprising an active region comprising a top surface, wherein the top surface comprises a first part and a second part; and an opaque layer covering the first part of the top surface and exposing the second part of the top surface, wherein the second part is directly above the first hole.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Inventors: Cheng-Feng YU, Ching-Yuan TSAI, Yao-Ru CHANG, Hsin-Chan CHUNG, Shih-Chang LEE, Wen-Luh LIAO, Cheng-Hsing CHIANG, Kuo-Feng HUANG, Hsu-Hsuan TENG, Hung-Ta CHENG, Yung-Fu CHANG
  • Publication number: 20190210639
    Abstract: A method of evaluating the health status of belt drive in electric power steering system by detecting the occurrence of sliding teeth in the electric power steering system and the frequency of occurrence and the output of the motor. In this way, the user really knows the belt drive health of the electric power steering system.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Eric WANG, Yi-Wei LIAO, Chun-Yu HUANG, Ming-Si YAN, Hsin-Fu WANG
  • Patent number: 10319877
    Abstract: The present disclosure provides a light-emitting device including a substrate, a first block of semiconductor stack on the substrate, a second block of semiconductor stack on the substrate and a third block of semiconductor stack on the substrate. The first block of semiconductor stack includes a first emitting wavelength and a first surface away from the substrate. The second block of semiconductor stack on the substrate includes a second emitting wavelength and a second surface away from the substrate. The third block of semiconductor stack includes s a third emitting wavelength and a third surface away from the substrate. The second surface and the first surface are non-coplanar and the third surface and the first surface are coplanar. The first emitting wavelength, the second emitting wavelength and the third emitting wavelength are different.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 11, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Fu Huang, Chih-Chiang Lu, Chun-Yu Lin, Hsin-Chih Chiu
  • Patent number: 10312407
    Abstract: A light-emitting device is provided. The light-emitting device comprises a substrate; an insulating layer on the substrate, wherein the insulating layer comprises a first hole; a light-emitting stack on the insulating layer and comprising an active region comprising a top surface, wherein the top surface comprises a first part and a second part; and an opaque layer covering the first part of the top surface and exposing the second part of the top surface, wherein the second part is directly above the first hole.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Feng Yu, Ching-Yuan Tsai, Yao-Ru Chang, Hsin-Chan Chung, Shih-Chang Lee, Wen-Luh Liao, Cheng-Hsing Chiang, Kuo-Feng Huang, Hsu-Hsuan Teng, Hung-Ta Cheng, Yung-Fu Chang
  • Patent number: 10290530
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20190122925
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10199269
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10199228
    Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
  • Publication number: 20180337187
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 22, 2018
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20180301458
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: March 15, 2018
    Publication date: October 18, 2018
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng