Patents by Inventor Hsin-Hao Huang

Hsin-Hao Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240130257
    Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.
    Type: Application
    Filed: April 21, 2023
    Publication date: April 18, 2024
    Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
  • Publication number: 20240113036
    Abstract: An electromagnetic interference (EMI) shielding package structure, a manufacturing method thereof, and an electronic assembly are provided. The EMI shielding package structure includes a carrier, at least one chip mounted on a first board surface of the carrier, an encapsulant formed on the carrier and packaging the at least one chip, an EMI shielding layer formed on an outer surface of the encapsulant, and an insulating layer. The insulating layer includes a spraying portion and a capillary permeating portion. The spraying portion is formed at least part of an outer surface of the EMI shielding layer. The capillary permeating portion is formed by extending from a bottom end of the spraying portion toward a second board surface of the carrier through capillarity, and the capillary permeating portion covers a bottom edge of the EMI shielding layer.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 4, 2024
    Inventors: CHIH-HAO LIAO, SHU-HAN WU, HSIN-YEH HUANG
  • Patent number: 11949016
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20240074041
    Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Gwo-Shyan Sheu, Kuo-Liang Huang, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma
  • Patent number: 11874545
    Abstract: A manufacturing method of an electronic device is provided. First, a mother panel including a first flexible mother board, a second flexible mother board and at least one sealing material is provided, and the sealing material is disposed between the first flexible mother board and the second flexible mother board. Then, a separating process including a laser-cutting process is performed to cut the first flexible mother board into a first flexible substrate and to cut the second flexible mother board into a second flexible substrate. The first flexible substrate includes a first laser-cutting buffer region and a first edge. The second flexible substrate includes a second laser-cutting buffer region and a second edge. The sealing material is away from the first edge by the first laser-cutting buffer region and away from the second edge by the second laser-cutting buffer region.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: January 16, 2024
    Assignee: InnoLux Corporation
    Inventors: Hsin-Hao Huang, Chu-Hong Lai
  • Patent number: 11812554
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11645953
    Abstract: The present disclosure provides a method for manufacturing the flexible display device. The method for manufacturing the flexible display device includes the following steps. First, a flexible substrate and a bonding structure are provided, in which the bonding structure is disposed on the flexible substrate. Subsequently, an anisotropic conductive film is provided on the bonding structure. Then, a driving circuit is provided on the anisotropic conductive film. Thereafter, the anisotropic conductive film is cured at a bonding temperature greater than or equal to 140° C. and less than or equal to 165° C.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 9, 2023
    Assignee: InnoLux Corporation
    Inventors: Hsin-Hao Huang, Chu-Hong Lai, Yu-Chih Tseng
  • Patent number: 11606860
    Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Gwo-Shyan Sheu, Hsin-Hao Huang, Yu-Chen Ma, Chia-Hsin Yen
  • Patent number: 11581283
    Abstract: A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Publication number: 20230044345
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a circuit layer, a flip-chip element and an anti-stress circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. Bonding circuits and transmission circuits of the circuit layer are disposed on the chip mounting area and the circuit area respectively. The flip-chip element is disposed on the chip mounting area and includes bumps and a chip having a long side margin and conductive pads, the bumps are provided to connect the conductive pads and the bonding circuits. Anti-stress circuits of the anti-stress circuit layer are disposed on the chip mounting area and parallel to the long side margin of the chip, and the bumps are located between the anti-stress circuits and the long side margin of the chip.
    Type: Application
    Filed: June 24, 2022
    Publication date: February 9, 2023
    Inventors: Yu-Chen Ma, Pei-Wen Wang, Hsin-Hao Huang, Gwo-Shyan Sheu
  • Publication number: 20220254282
    Abstract: The present disclosure provides a method for manufacturing the flexible display device. The method for manufacturing the flexible display device includes the following steps. First, a flexible substrate and a bonding structure are provided, in which the bonding structure is disposed on the flexible substrate. Subsequently, an anisotropic conductive film is provided on the bonding structure. Then, a driving circuit is provided on the anisotropic conductive film. Thereafter, the anisotropic conductive film is cured at a bonding temperature greater than or equal to 140° C. and less than or equal to 165° C.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: InnoLux Corporation
    Inventors: Hsin-Hao Huang, Chu-Hong Lai, Yu-Chih Tseng
  • Patent number: 11402680
    Abstract: The present disclosure provides an electronic device including a first flexible substrate, a second flexible substrate, a liquid crystal layer and a supporting structure. The second flexible substrate includes a first region and a second region. The first region overlaps with the first flexible substrate, and the second region does not overleap with the first flexible substrate. The liquid crystal layer is disposed between the first flexible substrate and the second flexible substrate. The supporting structure is disposed on the second region and includes a supporting film.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: August 2, 2022
    Assignee: InnoLux Corporation
    Inventors: Ming-Han Wu, Chien-Feng Li, Hsin-Hao Huang, Chu-Hong Lai
  • Publication number: 20220225496
    Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.
    Type: Application
    Filed: October 19, 2021
    Publication date: July 14, 2022
    Inventors: Gwo-Shyan Sheu, Hsin-Hao Huang, Yu-Chen Ma, Chia-Hsin Yen
  • Patent number: 11348489
    Abstract: The present disclosure provides a flexible display device and a method for manufacturing the flexible display device. The method for manufacturing the flexible display device includes the following steps. First, a flexible substrate and a bonding structure are provided, in which the bonding structure is disposed on the flexible substrate. Subsequently, an anisotropic conductive film is provided on the bonding structure. Then, a driving circuit is provided on the anisotropic conductive film. Thereafter, the anisotropic conductive film is cured at a bonding temperature greater than or equal to 140° C. and less than or equal to 165° C.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 31, 2022
    Assignee: InnoLux Corporation
    Inventors: Hsin-Hao Huang, Chu-Hong Lai, Yu-Chih Tseng
  • Patent number: 11322437
    Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 3, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11309238
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate, the circuit area surrounds the chip mounting area. The chip is mounted on the chip mounting area of the top surface and includes a bump. The circuit layer is disposed on the top surface. A connection portion of the circuit layer extends across a first side of the chip mounting area and into the chip mounting area. A transmission portion of the circuit layer is located on the circuit area and electrically connected to the connection portion. A stress release portion of the circuit layer is located between the transmission portion and a second side of the chip mounting area and is a comb-shaped structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 19, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Publication number: 20220113579
    Abstract: A manufacturing method of an electronic device is provided. First, a mother panel including a first flexible mother board, a second flexible mother board and at least one sealing material is provided, and the sealing material is disposed between the first flexible mother board and the second flexible mother board. Then, a separating process including a laser-cutting process is performed to cut the first flexible mother board into a first flexible substrate and to cut the second flexible mother board into a second flexible substrate. The first flexible substrate includes a first laser-cutting buffer region and a first edge. The second flexible substrate includes a second laser-cutting buffer region and a second edge. The sealing material is away from the first edge by the first laser-cutting buffer region and away from the second edge by the second laser-cutting buffer region.
    Type: Application
    Filed: December 19, 2021
    Publication date: April 14, 2022
    Applicant: InnoLux Corporation
    Inventors: Hsin-Hao Huang, Chu-Hong Lai
  • Publication number: 20220104354
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.
    Type: Application
    Filed: April 12, 2021
    Publication date: March 31, 2022
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu