Patents by Inventor Hsin-Hao YEH

Hsin-Hao YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261036
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20240379346
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20240347355
    Abstract: A method for using a system for annealing a wafer is provided. The method includes generating a laser beam by a laser beam generator. The method also includes projecting the laser beam with a first laser parameter onto a first semiconductor die of the wafer along at least one annealing orbit by a controller. Arranging a first annealing orbit to cover a source/drain region of a first transistor of the first semiconductor die and a second annealing orbit to cover a source/drain region of the first transistor of the first semiconductor die by the controller. A first gate electrode of the first transistor of the first semiconductor die is between and separated from the first annealing orbit and the second annealing orbit.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventor: Hsin-Hao YEH
  • Patent number: 12051603
    Abstract: Systems for annealing a wafer are provided. A system includes a wafer stage, a laser beam generator, and a controller. The laser beam generator is configured to generate a laser beam. The controller is configured to control the laser beam generator according to information regarding layout of a first semiconductor die of the wafer, so as to project the laser beam with a first laser parameter onto the first semiconductor die of the wafer on the wafer stage along at least one annealing orbit. The controller is configured to arrange the annealing orbit to partially cover the first semiconductor die of the wafer and to uncover a plurality of second semiconductor dies of the wafer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsin-Hao Yeh
  • Publication number: 20240097036
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Patent number: 11855213
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Publication number: 20230386826
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Patent number: 11830727
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20220336202
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20220231169
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Patent number: 11393674
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Patent number: 11296225
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Publication number: 20210257230
    Abstract: Systems for annealing a wafer are provided. A system includes a wafer stage, a laser beam generator, and a controller. The laser beam generator is configured to generate a laser beam. The controller is configured to control the laser beam generator according to information regarding layout of a first semiconductor die of the wafer, so as to project the laser beam with a first laser parameter onto the first semiconductor die of the wafer on the wafer stage along at least one annealing orbit. The controller is configured to arrange the annealing orbit to partially cover the first semiconductor die of the wafer and to uncover a plurality of second semiconductor dies of the wafer.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventor: Hsin-Hao YEH
  • Patent number: 11011394
    Abstract: A method for annealing a semiconductor die is provided. Information regarding layout of the semiconductor die is received. At least one annealing orbit on the semiconductor die is obtained according to the received information. An alignment procedure is performed on a plurality of alignment marks of the semiconductor die according to the received information. The semiconductor die is positioned according to the alignment marks. A laser beam with a first laser parameter is projected onto the positioned semiconductor die along the annealing orbit, so as to anneal a first portion of the positioned semiconductor die covered by the annealing orbit. The positioned semiconductor die is partially covered by the annealing orbit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsin-Hao Yeh
  • Patent number: 10868131
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Publication number: 20200044042
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Publication number: 20200006565
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 2, 2020
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Publication number: 20190386111
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Patent number: 10510861
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Publication number: 20190355570
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee