Patents by Inventor Hsin-Hao YEH
Hsin-Hao YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12261036Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: GrantFiled: July 25, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20240379346Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20240347355Abstract: A method for using a system for annealing a wafer is provided. The method includes generating a laser beam by a laser beam generator. The method also includes projecting the laser beam with a first laser parameter onto a first semiconductor die of the wafer along at least one annealing orbit by a controller. Arranging a first annealing orbit to cover a source/drain region of a first transistor of the first semiconductor die and a second annealing orbit to cover a source/drain region of the first transistor of the first semiconductor die by the controller. A first gate electrode of the first transistor of the first semiconductor die is between and separated from the first annealing orbit and the second annealing orbit.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Inventor: Hsin-Hao YEH
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Patent number: 12051603Abstract: Systems for annealing a wafer are provided. A system includes a wafer stage, a laser beam generator, and a controller. The laser beam generator is configured to generate a laser beam. The controller is configured to control the laser beam generator according to information regarding layout of a first semiconductor die of the wafer, so as to project the laser beam with a first laser parameter onto the first semiconductor die of the wafer on the wafer stage along at least one annealing orbit. The controller is configured to arrange the annealing orbit to partially cover the first semiconductor die of the wafer and to uncover a plurality of second semiconductor dies of the wafer.Type: GrantFiled: May 6, 2021Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Hsin-Hao Yeh
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Publication number: 20240097036Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Patent number: 11855213Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: GrantFiled: April 4, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Publication number: 20230386826Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Patent number: 11830727Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: GrantFiled: June 30, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20220336202Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20220231169Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Patent number: 11393674Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: GrantFiled: May 18, 2018Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Patent number: 11296225Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: GrantFiled: May 24, 2019Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Publication number: 20210257230Abstract: Systems for annealing a wafer are provided. A system includes a wafer stage, a laser beam generator, and a controller. The laser beam generator is configured to generate a laser beam. The controller is configured to control the laser beam generator according to information regarding layout of a first semiconductor die of the wafer, so as to project the laser beam with a first laser parameter onto the first semiconductor die of the wafer on the wafer stage along at least one annealing orbit. The controller is configured to arrange the annealing orbit to partially cover the first semiconductor die of the wafer and to uncover a plurality of second semiconductor dies of the wafer.Type: ApplicationFiled: May 6, 2021Publication date: August 19, 2021Inventor: Hsin-Hao YEH
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Patent number: 11011394Abstract: A method for annealing a semiconductor die is provided. Information regarding layout of the semiconductor die is received. At least one annealing orbit on the semiconductor die is obtained according to the received information. An alignment procedure is performed on a plurality of alignment marks of the semiconductor die according to the received information. The semiconductor die is positioned according to the alignment marks. A laser beam with a first laser parameter is projected onto the positioned semiconductor die along the annealing orbit, so as to anneal a first portion of the positioned semiconductor die covered by the annealing orbit. The positioned semiconductor die is partially covered by the annealing orbit.Type: GrantFiled: February 27, 2018Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Hsin-Hao Yeh
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Patent number: 10868131Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.Type: GrantFiled: October 14, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hao Yeh, Ching Yu Huang
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Publication number: 20200044042Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.Type: ApplicationFiled: October 14, 2019Publication date: February 6, 2020Inventors: Hsin-Hao Yeh, Ching Yu Huang
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Publication number: 20200006565Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: ApplicationFiled: May 24, 2019Publication date: January 2, 2020Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Publication number: 20190386111Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Hsin-Hao Yeh, Ching Yu Huang
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Patent number: 10510861Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.Type: GrantFiled: June 15, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hao Yeh, Ching Yu Huang
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Publication number: 20190355570Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee