Patents by Inventor Hsin Hsiang WANG

Hsin Hsiang WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor bank structure and semiconductor package structure
    Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11373956
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang, Chih-Wei Huang, Shiuan-Yu Lin
  • Semiconductor device package with conductive pillars and method for manufacturing the same
    Patent number: 11201110
    Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210217701
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min Lung HUANG, Hung-Jung TU, Hsin Hsiang WANG, Chih-Wei HUANG, Shiuan-Yu LIN
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210035899
    Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min Lung HUANG, Hung-Jung TU, Hsin Hsiang WANG
  • CAPACITOR BANK STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20190393297
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Chien-Hua CHEN, Teck-Chong LEE, Hung-Yi LIN, Pao-Nan LEE, Hsin Hsiang WANG, Min-Tzu HSU, Po-Hao CHEN