Patents by Inventor Hsin-Hsing Chen
Hsin-Hsing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937370Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.Type: GrantFiled: September 1, 2021Date of Patent: March 19, 2024Assignee: UNIFLEX Technology Inc.Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
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Publication number: 20220359411Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Yi-Chen HO, Chien Lin, Cheng-Yeh Yu, Hsin-Hsing Chen, Ju Ru Hsieh
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Patent number: 11450609Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.Type: GrantFiled: September 10, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Ho, Chien Lin, Cheng-Yeh Yu, Hsin-Hsing Chen, Ju Ru Hsieh
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Publication number: 20210375776Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.Type: ApplicationFiled: September 10, 2020Publication date: December 2, 2021Inventors: Yi-Chen Ho, Chien Lin, Cheng-Yeh Yu, Hsin-Hsing Chen, Ju Ru Hsieh
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Patent number: 9548268Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.Type: GrantFiled: June 4, 2015Date of Patent: January 17, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Chi Huang, Yung-Hung Yen, Hsin-Hsing Chen, Chih-Yueh Li, Tsun-Min Cheng
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Publication number: 20160322299Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.Type: ApplicationFiled: June 4, 2015Publication date: November 3, 2016Inventors: Chun-Chi Huang, Yung-Hung Yen, Hsin-Hsing Chen, Chih-Yueh Li, Tsun-Min Cheng
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Patent number: 8350334Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.Type: GrantFiled: June 13, 2011Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Min Wang, An-Chi Liu, Hsin-Hsing Chen, Chih-Chun Wang
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Publication number: 20120313181Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Min Wang, An-Chi Liu, Hsin-Hsing Chen, Chih-Chun Wang
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Patent number: 7872292Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.Type: GrantFiled: February 21, 2006Date of Patent: January 18, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang
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Publication number: 20080113481Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.Type: ApplicationFiled: January 15, 2008Publication date: May 15, 2008Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang
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Publication number: 20080067145Abstract: A method of recycling dummy wafer is provided. The dummy wafer has at least one low-k dielectric material layer formed thereon. A treatment process is performed to the low-k dielectric material layer on the dummy wafer so that a component or impurity in the low-k dielectric material layer reacts to form a volatile substance. A wet etching process is performed to remove the low-k dielectric material layer.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chun Wang, Chia-Pin Lee, Chun-Yuan Wu, Hsien-Che Teng, Hsin-Hsing Chen, Yu-Cheng Lin
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Publication number: 20080026579Abstract: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the copper damascene process are removed by the heat treatment, therefore the copper damascene structure is completely reduced by the reduction plasma treatment and is improved.Type: ApplicationFiled: July 25, 2006Publication date: January 31, 2008Inventors: Kuo-Chih Lai, Mei-Ling Chen, Jei-Ming Chen, Hsin-Hsing Chen, Shih-Feng Su, Meng-Chi Chen
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Publication number: 20070196977Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang