Patents by Inventor Hsin Hsiung

Hsin Hsiung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959318
    Abstract: An oven includes an oven body, a heating element, a frame, and an oven door. The oven body has an inner space inside and includes a front plate, wherein the front plate has an entrance that communicates with the inner space. The heating element is adapted to heat the inner space. The frame is engaged with the oven body and has an abutted portion. The oven door is pivotally connected to the oven body and is located at the entrance. The oven door can pivot to a closed position to close the entrance and can pivot downward to an open position from the closed position to open the entrance. When the oven door is located at the open position, the second surface abuts against the abutted portion of the frame, thereby forming a platform outside the entrance for placing objects.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: April 16, 2024
    Assignee: GRAND MATE CO., LTD.
    Inventors: Chung-Chin Huang, Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh
  • Publication number: 20240043443
    Abstract: Compounds and methods of modulating 15-PGDH activity, modulating tissue prostaglandin levels, treating disease, diseases disorders, or conditions in which it is desired to modulate 15-PGDH activity and/or prostaglandin levels include 15-PGDH inhibitors and 15-PGDH activators described herein.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 8, 2024
    Inventors: Sanford Markowitz, James K.V. Willson, Bruce Posner, Joseph Ready, Yongyou Zhang, Hsin-Hsiung Tai, Monica Antczak, Stanton Gerson, KiBeom Bae, Sung Yeun Yang, Amar Desai
  • Patent number: 11256838
    Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.
    Type: Grant
    Filed: May 3, 2020
    Date of Patent: February 22, 2022
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 11144697
    Abstract: A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 12, 2021
    Assignee: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Hsin-Hsiung Yu, Ching-Chong Chuang, Chung-Ching Tseng
  • Publication number: 20210303767
    Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.
    Type: Application
    Filed: May 3, 2020
    Publication date: September 30, 2021
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20210032265
    Abstract: Compounds and methods of modulating 15-PGDH activity, modulating tissue prostaglandin levels, treating disease, diseases disorders, or conditions in which it is desired to modulate 15-PGDH activity and/or prostaglandin levels include 15-PGDH inhibitors and 15-PGDH activators described herein.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Inventors: Sanford Markowitz, James K.V. Willson, Bruce Posner, Joseph Ready, Yongyou Zhang, Hsin-Hsiung Tai, Monika Antczak, Stanton Gerson, KiBeom Bae, Sung Yeun Yang, Amar Desai
  • Patent number: 10817633
    Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 27, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20200311218
    Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 1, 2020
    Inventors: Meng-Hsiu TSAI, Hsin-Hsiung LIAO, Min-Hsiu TSAI
  • Patent number: 10772940
    Abstract: The presently-disclosed subject matter includes isolated polypeptides that comprise a butyrylcholinestrase (BChE) polypeptide and a second polypeptide. The BChE polypeptide as well as the second polypeptide can be variants and/or fragments thereof. The presently-disclosed subject matter also includes a pharmaceutical composition that comprises the present isolated polypeptide and a suitable pharmaceutical carrier. Further still, methods are provided for treating cocaine-induced conditions, and comprise administering the isolated polypeptide and/or pharmaceutical compositions thereof to an individual.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 15, 2020
    Assignee: University of Kentucky Research Foundation
    Inventors: Chang-Guo Zhan, Fang Zheng, Hsin-Hsiung Tai, Xiabin Chen, Liu Xue, Shurong Hou
  • Publication number: 20200140453
    Abstract: Compounds and methods of modulating 15-PGDH activity, modulating tissue prostaglandin levels, treating disease, diseases disorders, or conditions in which it is desired to modulate 15-PGDH activity and/or prostaglandin levels include 15-PGDH inhibitors and 15-PGDH activators described herein.
    Type: Application
    Filed: May 24, 2019
    Publication date: May 7, 2020
    Inventors: Sanford Markowitz, James K.V. Willson, Bruce Posner, Joseph Ready, Youngyou Zhang, Hsin-Hsiung Tai, Monika Antczak, Stanton Gerson, KiBeom Bae, Sung Yeun Yang, Amar Desai
  • Patent number: 10614260
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 7, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 10498034
    Abstract: An antenna module is disclosed. The antenna module includes a circuit board and at least one antenna set. Wherein, the antenna set includes a driving antenna and a plurality of parasitic antennas. The driving antenna is formed on the circuit board, and the parasitic antennas are positioned with the driving antenna as a center on the circuit board. Whereby, the space occupied by the antenna module can be small, and beams of wireless signals radiated by the antenna module can be controlled.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 3, 2019
    Assignee: ACCTON TECHNOLOGY CORPORATION
    Inventors: I-Ru Liu, Yen-Lin Liao, Hsin-Hsiung Kang, Li-Hua Chou, Wen-Pin Lo, Chun-Yi Kuo, Chang-Cheng Liu
  • Publication number: 20190294746
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 26, 2019
    Inventors: Meng-Hsiu TSAI, Hsin-Hsiung LIAO, Min-Hsiu TSAI
  • Patent number: 10411352
    Abstract: The present invention discloses an antenna tuning system and method thereof. The method comprises the following steps: choosing a parasitic antenna that combined with a main antenna, the strongest received signal strength indicator of a target station is detected; controlling the selected parasitic antenna that combined with a main antenna, to generate a scattering resonance through turning on or off a switch unit; and controlling a diffraction radiation pattern between the main antenna and the selected parasitic antenna through adjusting a load of a designed circuit.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 10, 2019
    Assignee: ACCTON TECHNOLOGY CORPORATION
    Inventors: I-Ru Liu, Wen-Pin Lo, Hsin-Hsiung Kang, Yang-Te Fu, Chang-Cheng Liu, Yen-Lin Liao, Yi-Chang Chen, Li-Hua Chou
  • Patent number: 10311185
    Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 4, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 10301320
    Abstract: Compounds and methods of modulating 15-PGDH activity, modulating tissue prostaglandin levels, treating disease, diseases disorders, or conditions in which it is desired to modulate 15-PGDH activity and/or prostaglandin levels include 15-PGDH inhibitors and 15-PGDH activators described herein.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: May 28, 2019
    Assignees: University of Kentucky Research Foundation, Case Western Reserve University, Board of Regents of the University of Texas System
    Inventors: Sanford Markowitz, James K. V. Willson, Bruce Posner, Joseph Ready, Youngyou Zhang, Hsin-Hsiung Tai, Monika Antczak, Stanton Gerson, KiBeom Bae, Sung Yeun Yang, Amar Desai
  • Patent number: 10275159
    Abstract: An embedded device, a RAM disk of an embedded device and a method of accessing a RAM disk of an embedded device are provided. The embedded device includes: a processing unit, configured to execute an operating system; a first memory, for the processing unit to access required system data when the processing unit executes the operating system; a function module, configured to perform a predetermined function; a second memory, for the function module to access required functional data through direct memory access when the function module performs the predetermined function; and a RAM disk driving module, configured to incorporate a first part of the first memory with the second memory to one RAM disk, and to control access of the RAM disk.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 30, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chien-Hsing Huang, Hsin-Hsiung Tseng
  • Patent number: 10276747
    Abstract: A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 30, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Kai Shen Chen, Hsin Hsiung Huang, Wan Jung Lee, Pei Chia Chen, Yung Hsin Tai
  • Patent number: 10243099
    Abstract: A semiconductor device comprises a substrate comprising a surface area having a plurality of patterns therein, wherein the plurality of patterns comprises a plurality of first patterns and a plurality of second patterns; and a light-emitting stack formed on the substrate; wherein each of the first patterns comprises a first feature length and each of the second patterns comprises a second feature length smaller than the first feature length, and wherein, in a square area of 30 microns by 30 microns chosen from the surface area, an amount of the plurality of the first patterns is more than that of the plurality of the second patterns.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 26, 2019
    Assignees: Epistar Corporation, Asahi Kasei Corporation
    Inventors: Jennhwa Fu, Hsin-Hsiung Huang, Mei-Li Wang
  • Publication number: 20180337304
    Abstract: A semiconductor device comprises a substrate comprising a surface area having a plurality of patterns therein, wherein the plurality of patterns comprises a plurality of first patterns and a plurality of second patterns; and a light-emitting stack formed on the substrate; wherein each of the first patterns comprises a first feature length and each of the second patterns comprises a second feature length smaller than the first feature length, and wherein, in a square area of 30 microns by 30 microns chosen from the surface area, an amount of the plurality of the first patterns is more than that of the plurality of the second patterns.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 22, 2018
    Inventors: Jennhwa FU, Hsin-Hsiung HUANG, Mei-Li WANG