Patents by Inventor Hsin Hsu

Hsin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12236180
    Abstract: A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 12223251
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang, Hsien-Hsin Sean Lee
  • Publication number: 20250048706
    Abstract: A sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. The sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. The sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. The sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. Thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 6, 2025
    Inventors: Tsung-Jui WU, Tsung-Yin HSU, Ying Ming WANG, Shih-Hao CHEN, Sung-Hsin YANG
  • Publication number: 20250048256
    Abstract: A method performed by a User Equipment (UE) for Network Energy Saving (NES) is provided. The method receives, from a Base Station (BS), a Radio Resource Control (RRC) message including an NES configuration. The method then determines whether to apply a cell Discontinuous Transmission (DTX) operation, a cell Discontinuous Reception (DRX) operation, or both the cell DTX operation and the cell DRX operation based on the NES configuration.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 6, 2025
    Inventors: TZU-WEN CHANG, CHIE-MING CHOU, YUNG-LAN TSENG, YEN-HUA LI, CHIA-HSIN LAI, CHUN-YEN HSU
  • Publication number: 20250040276
    Abstract: An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.
    Type: Application
    Filed: September 6, 2023
    Publication date: January 30, 2025
    Applicant: Powertech Technology Inc.
    Inventor: Hung-Hsin HSU
  • Publication number: 20250038641
    Abstract: A voltage regulator with diode retention is shown, which includes an input terminal receiving a supply voltage, an output terminal providing a regulated voltage, and a main circuit coupled between the input terminal and the output terminal. In a normal mode, the main circuit transforms the supply voltage to a first voltage as the regulated voltage. In a sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator, to generate a second voltage as the regulated voltage. The second voltage is lower than the first voltage.
    Type: Application
    Filed: July 5, 2024
    Publication date: January 30, 2025
    Inventors: Chung-Wei HSU, Wei-Hsin TSENG
  • Patent number: 12210295
    Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Chang Hsu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20250025028
    Abstract: A multichannel endoscope system includes a light module configured to emit illumination light on an object, an image module configured to capture an image of the object, and a multichannel sensor module configured to obtain a spectral information of the object. The multichannel sensor module includes an image lens, a light homogenizer and a multichannel array sensor, where the light homogenizer is formed between the multichannel array sensor and the image lens.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Jau-Jan Deng, Chang-Long Chen, Shih-Hsin Hsu
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20250022789
    Abstract: A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. The stress buffer pads may additionally improve an insertion loss characteristic of the package substrate. Accordingly, semiconductor package performance, reliability and yields may be improved.
    Type: Application
    Filed: July 31, 2024
    Publication date: January 16, 2025
    Inventors: Chung-Hsin Chen, Chi Wei Hsu, Sih Han Chen, Yi Chung Chen
  • Publication number: 20250022810
    Abstract: A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. Accordingly, semiconductor package reliability and yields may be improved.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 16, 2025
    Inventors: Chung-Hsin Chen, Chi Wei Hsu, Sih Han Chen, Yi Chung Chen
  • Patent number: 12198540
    Abstract: A message transmission method for a roadside equipment includes the following steps. A plurality of external sensor information is received. A road intersection sign phase information and a road map information are inputted. An object position analysis, a speed analysis, and an sign analysis in object moving direction are performed based on the external sensor information, the road intersection sign phase information, and the road map information, and a classification of dangerous objects in different groups is outputted. According to a current transmission bandwidth limitation and the classification of the dangerous objects, a dangerous object message with a higher classification of the dangerous objects is preferentially selected and transmitted within available transmission bandwidth.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 14, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shi-Xin Chen, Te-Hsuan Liu, Wei-Hsin Hsu, Qin Wang, Chun-Che Chang, Jing-Shyang Hwu
  • Patent number: 12154863
    Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: November 26, 2024
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 12111503
    Abstract: The fiber optic connector includes a connector head module, a mounting seat, a rear boot, an engaging module and a sheath member. The mounting seat is mounted to a rear end of the connector head module, and includes an external threaded portion. The rear boot is connected to a rear end of the mounting seat. The engaging module is removably coupled to the connector head module. The sheath member includes an internal threaded portion that is formed in an inner surface of the sheath member. When the engaging module is removed from the connector head module, the sheath member can be attachable to the mounting seat with the external threaded portion being threadedly engaged with the external threaded portion of the mounting seat.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: October 8, 2024
    Assignees: Gloriole Electroptic Technology Corp., Shen Zhen Wonderwin Technology Co., Ltd.
    Inventors: Hsien-Hsin Hsu, Yen-Chang Lee, Ke Xue Ning
  • Publication number: 20240329327
    Abstract: A fiber optic adapter includes a shielding casing that is connected to a casing body and that defines a through channel. Two engagement members extend from a casing body and extend through the through channel. A pivot shaft engages the shielding casing. A shielding plate is connected to the pivot shaft. A restoring member is sleeved on the pivot shaft. The shielding plate is pivotable about the pivot shaft against a resilient force of the restoring member from a shielding position to an open position relative to the shielding casing. When the shielding plate is in the shielding position, the shielding plate is disposed between the engagement members and shields the through channel. When the shielding plate is in the open position, the shielding plate opens the through channel.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 3, 2024
    Inventors: Hsien-Hsin HSU, Wu-Li CHU, Yen-Chang LEE, Shu-Bin LI
  • Patent number: 12092887
    Abstract: A fiber optic distribution frame includes a casing and a plurality of tray units disposed in the casing. Each tray unit includes a partition plate, a plurality of inner guiding rails disposed on the partition plate, and a plurality of mounting seats each disposed between adjacent two of the inner guiding rails and movable forwardly and rearwardly to be removed from the adjacent two of the inner guiding rails.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: September 17, 2024
    Assignee: GLORIOLE ELECTROPTIC TECHNOLOGY CORP.
    Inventor: Hsien-Hsin Hsu
  • Patent number: 12092886
    Abstract: An optical fiber distribution frame includes a casing and a plurality of tray units disposed in the casing. Each tray unit includes a partition plate, a plurality of inner guiding rails disposed on the partition plate, a plurality of mounting seats each removably disposed between adjacent two of the inner guiding rails, and a plurality of cable management members disposed respectively in front of the inner guiding rails and each including a lower clamp portion fixed to the partition plate, and an upper clamp portion cooperating with the lower clamp portion to define a cable accommodating space, having one end that cooperates with one end of the lower clamp portion to define an open slot in spatial communication with the cable accommodating space, and operable to adjust a dimension of the open slot to allow or prevent removal of optical fibers from the cable accommodating space.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: September 17, 2024
    Assignee: GLORIOLE ELECTROPTIC TECHNOLOGY CORP.
    Inventor: Hsien-Hsin Hsu
  • Patent number: 12087579
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Patent number: 12013576
    Abstract: An optical fiber adapter includes a housing, a positioning member disposed in the housing, and a clip member removably disposed in the housing. The housing includes two outer walls each formed with slots, two side walls each connected between the outer walls, and latches extending from a corresponding one of the outer walls into a corresponding one of the slots. The clip member includes a base portion, two connection portions disposed on two opposite ends of the base portion, and two pairs of clip arm portions extending from the connection portions. Each connection portion has an engaging groove engaged with a respective one of the latches.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: June 18, 2024
    Assignee: GLORIOLE ELECTROPTIC TECHNOLOGY CORP.
    Inventor: Hsien-Hsin Hsu
  • Patent number: D1047897
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 22, 2024
    Assignee: GOGORO INC.
    Inventors: Chien-Chih Weng, Chen-Hsin Hsu, Yu-Jung Wang