Abstract: The present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier. The plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on a second substrate within a second IC tier that is bonded to the first IC tier. A plurality of logic devices are disposed within a third IC tier that is bonded to the second IC tier. A through substrate via (TSV) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.

Abstract: A transistor device includes a substrate and a transistor. The transistor is disposed on the substrate and includes a gate, a gate dielectric layer, a semiconductor layer, a source and a drain. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer, and includes a first region and a second region. The first region at least partially overlaps with the gate in a normal direction of the substrate, the second region extends from the first region to an edge of the semiconductor layer, and the second region further includes a dopant compared to the first region. The source and the drain are disposed on the semiconductor layer, and are electrically connected to the second region of the semiconductor layer. At least one of the source and the drain does not overlap with the gate in the normal direction of the substrate.

Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.

Abstract: Exhibiting devices, uploading devices and viewing devices are connected to a server. At least one of the uploading devices uploads at least one image of at least one work of art. At least one of the exhibiting devices to uploads at least one image of at least one exhibition site. The server integrates the image of the work of art with the image of the exhibition site. The server announces exhibition of the work of art on the exhibition site. At least one of the viewing devices searches for the exhibition. The server generates an electronic map to show the location of the exhibition. The server pushes an assignment about the exhibition. At least one of the viewing devices finishes the assignment. The exhibiting, uploading or viewing device reports the finishing of the assignment to the server. The server updates data and sends the updated data to the exhibiting devices, the uploading devices and the viewing devices.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a memory stacking pair. The memory stacking pair includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. The first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes an upper surface; a plurality of exposed regions, formed in the semiconductor stack and exposing the upper surface; a lower protective layer, covering the exposed regions and the second semiconductor layer; a first reflective structure, formed on the second semiconductor layer and including a plurality of first openings on the second semiconductor layer; a second reflective structure, formed on the first reflective structure and electrically connected to the second semiconductor layer through the plurality of first openings; and an upper protective layer, formed on the second reflective structure; wherein the upper protective layer contacts and overlaps the lower protective layer on the exposed regions; wherein the first reflective structure and the

Abstract: To trade shares of a work of art, buyer and seller terminals are connected to a trading server. The seller terminal is used to post a work of art, set a type of right of the work of art, a type of an object of trade, a share of the work of art, a trade mode and seller's terms. The trading platform is used to display the work of art. The buyer terminal is used to search for the work of art and set buyer's terms. The trading server is used to match a buyer with a seller based on the seller's and buyer's terms. The trading server is used to execute a profit-sharing program and record an event of trade of the work of art.

Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.

Abstract: An electronic device is disclosed, which includes: a support unit; a display panel disposed on the support unit; a first circuit board, wherein the support unit is disposed between the display panel and the first circuit board; an electronic component disposed on the first circuit board; and a second circuit board electrically connected to the display panel, wherein the first circuit board is electrically connected to the display panel through the second circuit board, wherein the first circuit board includes a protruding section, and the electronic component is disposed on the protruding section.

Abstract: An electronic device includes a housing and a state indication light. The state indication light is assembled to the housing and includes a light-guiding structure and multiple light-emitting elements. The light-guiding structure has an incident plane, a reflection plane and an exit plane. The reflection plane is inclined to the incident plane and the exit plane. The light-emitting elements are disposed on a side of the light-guiding structure and face the incident plane. A light beam emitted by each of the light-emitting elements is adapted to enter the light-guiding structure from the incident plane and arrive at the reflection plane. The reflection plane is adapted to reflect the light beam towards the exit plane so that the light beam is directed from the exit plane to an outside of the light-guiding structure.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: A package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. A diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

Abstract: An electronic device includes a light guide plate, a back plate, a plurality of light sources, an optical film and a buffer member. The back plate accommodates the light guide plate and includes a bottom plate, a side plate, a bending portion and a first notch portion, wherein a side of the bending portion and a side of the bottom plate are respectively connected to opposite sides of the side plate, the bending portion is overlapped with the bottom plate, the first notch portion is adjacent to the bending portion, and the first notch portion is overlapped with the bottom plate. The light sources are disposed between the bottom plate and the bending portion. The optical film is disposed on the light guide plate and is separated from the bending portion. The buffer member is overlapped with the first notch portion and the light guide plate.

Abstract: A control valve includes a valve body and a valve gate. The valve gate is movably located inside the inner space. The control valve has a lower flow rate limit which is greater than zero. That is, the lower flow rate limit has no necessary to be zero, thus it is acceptable to have a cylindrical valve gate but not a spherical valve gate, and a diameter of the cylindrical valve gate is be smaller than a caliber of an opening of the valve body. Therefore, the valve gate can be directly installed into the valve body via the opening, which allows the valve body to be made of a single piece so as to simplify the processes of manufacturing and assembly.

Abstract: Whether a voltage difference reaches a hysteresis voltage of a hysteresis comparator is used to efficiently update a charge of a capacitor and achieve lower power consumption. On the other hand, since the advanced voltage holding circuit is designed to consume lower power, the refresh time must be designed longer, which makes it impossible to do a large number of yield tests. Thus, the test time in conjunction with the relevant application circuit can be greatly shortened, and the testability and reliability of a voltage holding device can be increased.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.