Abstract: Provided are systems and methods for a scalable configurable chip architecture. The system includes a first cluster and a second cluster multi-chip modules, and a data network coupling the first cluster to the second cluster. Each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chips coupled together by a first interconnect, each chip of the first plurality of chips configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle (AV). Each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chips coupled together by a second interconnect, each chip of the second plurality of chips configured to facilitate processing of at least one function of a second set of functions of the AV.

Abstract: In an embodiment, a method comprises: running, with a first core of a first multiprocessor system on chip (MPSoC) of a distributed computing architecture, a first process/thread on input data, the first process/thread pinned to the first core; storing, using a cache coherency fabric, first data in shared memory, the first data generated by the first process/thread; fetching, with a second process/thread pinned to a second core of a second MPSoC of the distributed computing architecture, the first data from the shared memory; and running, with the second core of the second MPSoC, the second process/thread on the first data.

Abstract: Multiple intertwined inductor coils combine to form one or more transformer devices of a semiconductor device. The intertwined inductor coils are formed of only two metallization layers and vias coupling the layers. The inductor coils are vertically oriented and include a magnetic axis parallel to the substrate surface. A plurality of metal wires are provided on both a first device level and a second device level. Each of the metal wires on the first device level is coupled to two wires on the second device level and forms a first inductor coil. The two metal wires on the second device level that form part of the first inductor coil, are separated by a third wire that is coupled to two different first device level metal wires and forms part of a different second inductor coil intertwined with the first inductor coil.

Abstract: MIM capacitors that are temperature and/or voltage independent, and a methodology for formulating the MIM capacitors for use in semiconductor integrated circuits, is provided. Vertical MIM capacitive structures include at least two vertically separated electrodes and a capacitor dielectric that includes portions of different dielectric materials provided in a desired area ratio. The disclosure provided for selecting dielectrics and dielectric thicknesses, determining an area ratio that produces temperature and/or voltage independent MIM capacitors, and forming capacitive devices with the desired area ratio. In one embodiment, the capacitor dielectric includes at least one SiO dielectric portion and at least one SiN dielectric portion and a total capacitive area includes the SiN and SiO dielectric portions arranged such that the ratio of the area of the SiO portions to the area of the SiN portions is about 1.15:1.

Abstract: Multiple intertwined inductor coils combine to form one or more transformer devices of a semiconductor device. The intertwined inductor coils are formed of only two metallization layers and vias coupling the layers. The inductor coils are vertically oriented and include a magnetic axis parallel to the substrate surface. A plurality of metal wires are provided on both a first device level and a second device level. Each of the metal wires on the first device level is coupled to two wires on the second device level and forms a first inductor coil. The two metal wires on the second device level that form part of the first inductor coil, are separated by a third wire that is coupled to two different first device level metal wires and forms part of a different second inductor coil intertwined with the first inductor coil.

Abstract: A split-gate flash cell device and method for forming the same are not provided. The split-gate flash cell device includes a floating gate transistor. The floating gate transistor includes a floating gate and a control gate disposed over at least a portion of the floating gate, along a side of the floating gate and over a portion of the substrate adjacent the floating gate. The control gate includes a portion of SiGe material. In some embodiments, the control gate is a composite material with a lower SiGe layer and an upper material layer. The upper material layer is polysilicon or other suitable materials.

Abstract: A H-sync phase locked loop device for TV video signal is provided herein. After the TV video signal is digitalized, clamping and slicing operations are performed on the digitalized TV video signal to respectively generate a clamped signal and a sliced signal. According to the clamped signal and the sliced signal, an H-sync frequency calculator can calculate the falling and rising transients of the H-sync signal and an H-sync frequency is obtained therefrom. Because the H-sync frequency is dynamically adjusted according to the input TV video signal, the phase locking of the input TV video signal can tolerate more deviations of the H-sync by replacing a predetermined H-sync frequency.

Abstract: A H-sync phase locked loop device for TV video signal is provided herein. After the TV video signal is digitalized, clamping and slicing operations are performed on the digitalized TV video signal to respectively generate a clamped signal and a sliced signal. According to the clamped signal and the sliced signal, an H-sync frequency calculator can calculate the falling and rising transients of the H-sync signal and an H-sync frequency is obtained therefrom. Because the H-sync frequency is dynamically adjusted according to the input TV video signal, the phase locking of the input TV video signal can tolerate more deviations of the H-sync by replacing a predetermined H-sync frequency.