Abstract: An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.

Abstract: A converter that converts a differential input signal to a single-end output signal is provided. The converter includes first, second, third and fourth transistors, and a pair of current sources. The first and second transistors are driven by the differential input signal, and have two conduction nodes coupled to each other and two conduction nodes not coupled to each other. The third and fourth transistors are driven by the differential input signal, and are connected in series with the first and second transistors. The pair of current sources, respectively connected in series with the third and fourth transistors, have a common control node coupled to the second conduction node of the first transistor. The second conduction node of the second transistor generates the single-end output signal.

Abstract: An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.

Abstract: A converter that converts a differential input signal to a single-end output signal is provided. The converter includes first, second, third and fourth transistors, and a pair of current sources. The first and second transistors are driven by the differential input signal, and have two conduction nodes coupled to each other and two conduction nodes not coupled to each other. The third and fourth transistors are driven by the differential input signal, and are connected in series with the first and second transistors. The pair of current sources, respectively connected in series with the third and fourth transistors, have a common control node coupled to the second conduction node of the first transistor. The second conduction node of the second transistor generates the single-end output signal.

Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.

Abstract: A memory device includes a global decoder circuit and two memory cell array devices, each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit. Each of two data input buffers is disposed at a third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, and is coupled to the respective one of the memory cell arrays. A write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. A write clock buffer is disposed adjacent to the third side of the global decoder circuit, and is coupled to the data input buffers. A read control circuit is coupled to and is disposed adjacent to a fourth side of the global decoder circuit. Each of two multiplexer sets is coupled to bit lines of a respective one of the memory cell array devices.