Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

Abstract: A method of a fault detection and classification (FDC) may be used to determine outlier tools from a plurality of tools. The method includes generating a plurality of parameter charts, generating a plurality of group charts according to the plurality of parameter charts, generating a score table according to the plurality of group charts, determining outlier tools according to the score table, and performing tool correction on the outlier tools.

Abstract: A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.

Abstract: A complex chemical mechanical polishing process for planarizing a structure. The process comprises steps of performing a main polishing process with a first polishing rate, wherein a slurry is provided. An assisted polishing process is then performed to planarizing the structure. The assisted polishing process comprises steps of providing the slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate.

Abstract: A hybrid CMP system having a first platen and a second platen is provided. Two types of polish pads are mounted on the first platen and second platen. A lot of pattern wafers is prepared. Each pattern wafer has patterned features, and a first dielectric layer is disposed over a second dielectric layer and the patterned features. At least three foregoing pattern wafers of the lot are sequentially polished on the first platen to remove different amount of the first dielectric layer. Removal amount of each said foregoing pattern wafer is in-line measured and calculated to output a linear fitting curve of removal amount vs. polish time thereof. Based on the linear fitting curve, the rest of the pattern wafers of the same lot are sequentially polished on the first platen to reach a target thickness of remaining said first dielectric layer.

Abstract: A cleaning method according to the present invention is provided. The method includes at least two stages of cleaning processes. In the first stage, dilute HF is provided as a cleaning solution, and a brushing process is performed. In the second stage, dilute HF is also provided as a cleaning solution, and a washing process is performed. A pre-cleaning process and a post-cleaning process are further provided according to the present invention. The pre-cleaning method is performed before the brushing process, and the post-cleaning method is performed after the washing process. In addition, the pre-cleaning process and the post-cleaning process are a brushing process or a washing process adopting NH4OH as a cleaning solution.

Abstract: Disclosed is a method for improving HSS CMP performance. After performing a HSS CMP process for a predetermined time, DI water is introduced and the polishing process is continued, so that the CMP rate and performance can be improved.

Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed on a substrate. A node contact opening is formed in the dielectric layer to expose a portion of the substrate. A conductive layer is formed on the dielectric layer to cover the node contact opening. A ring trench is formed in the conductive layer above the node contact opening. An oxide layer is formed to fill the ring trench. An etching stop layer is formed to cover the oxide layer, the conductive layer encircled by the oxide layer, and a portion of the oxide layer beside the oxide layer. The etching stop layer defines a capacitor area. The conductive layer exposed by the etching stop layer is removed until the dielectric layer is exposed. The oxide layer and the etching stop layer are removed to expose the remaining conductive layer. A capacitor dielectric layer and a top electrode are formed in sequence to cover the remaining conductive layer.

Abstract: A method of fabricating a DRAM capacitor. After forming a node contact opening in a dielectric layer on the substrate, a conductive layer having an annulus hollow is formed. A recess is formed on the conductive layer and a spacer is formed on the sidewall of the spacer, after which the annulus hollow is filled with an oxide layer. A photoresist layer for defining the capacitor region is formed. The etching stop layer, the oxide layer, and the spacer are removed to form the bottom electrode. Then, the dielectric layer and the upper electrode are formed in sequence.

Abstract: An apparatus and method for performing a chemical vapor deposition (CVD) procedure to deposit an insulating layer when fabricating semiconductor integrated circuit devices over a silicon wafer. The CVD apparatus includes a buffer chamber for temporarily holding the wafer, and a chemical vapor deposition reaction chamber arranged at the periphery of the buffer chamber and communicating with the buffer chamber via a first access door. The CVD apparatus additionally includes a heating chamber, also arranged at the periphery of the buffer chamber, and communicating with the buffer chamber via a second access door, for performing a heating treatment of the wafer before the insulating layer is deposited on the wafer in the CVD reaction chamber. A transport arm is provided for transporting the wafer into and out of the heating chamber and the chemical vapor deposition reaction chamber.