Patents by Inventor Hsin-Liang Chen
Hsin-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9349830Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.Type: GrantFiled: March 5, 2013Date of Patent: May 24, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing-Chor Chan, Hsin-Liang Chen
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Publication number: 20160126237Abstract: A semiconductor device including metal-on-semiconductor (MOS) and bipolar junction (BJ) structures formed in a substrate. The MOS structure includes a first region, a second region formed over the first region, a third region, and a fourth region formed over the third region. The first, second, and fourth regions have a first-type conductivity, being drain region, drain electrode, and source region of the MOS structure. Doping level of the second region is higher than that of the first region. The third region has a second-type conductivity, including channel and body regions of the MOS structure. The channel region is formed between the first and fourth regions. The BJ structure includes a fifth region formed over the first region, contacting the second region, having the second-type conductivity, and being an emitter region of the BJ structure. The second and third regions are base and collector regions of the BJ structure.Type: ApplicationFiled: November 4, 2014Publication date: May 5, 2016Inventors: Hsin-Liang CHEN, Ying-Chieh TSAI, Wing-Chor CHAN, Shyi-Yuan WU
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Patent number: 9263432Abstract: A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.Type: GrantFiled: May 6, 2014Date of Patent: February 16, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 9263429Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.Type: GrantFiled: August 19, 2013Date of Patent: February 16, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 9250648Abstract: A memory expansion assembly includes a first plate having first electrical slots and a first electrically connecting portion, a second plate pivotally connected to the first plate and having second electrical slots and a second electrically connecting portion, a first engaging assembly, and a second engaging assembly. The first electrical slots are electrically connected to the first electrically connecting portion. The second electrical slots are electrically connected to the second electrically connecting portion. The second plate is adapted to pivot relative to the first plate to have a folded position when the two are close to each other and an unfolded position when the two are away from each other. The first engaging assembly is disposed on a side of the first plate. The second engaging assembly is disposed on a side of the second plate. The first engaging assembly is removably engaged with the second engaging assembly.Type: GrantFiled: March 16, 2013Date of Patent: February 2, 2016Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Ming-Hung Shih, Hsin-Liang Chen, Yen-Cheng Lin
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Publication number: 20160027773Abstract: A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity.Type: ApplicationFiled: July 25, 2014Publication date: January 28, 2016Inventors: Hsin-Liang CHEN, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 9223358Abstract: A foldable assembly includes a first plate component, a second plate component and a pivot assembly. The pivot assembly comprises a first pivot member, a second pivot member and a third pivot member. The first pivot member and the second pivot member are connected with the first plate component and the second plate component, respectively. Each of the first pivot member and the second pivot member has an axial hole and a plurality of recesses. Each of the two opposite sides of the third pivot member has a shaft and a protrusion located on an outer wall surface of the shaft. The two shafts are adapted for being rotatable on the two axial holes, respectively. The two protrusions are located on one of the plurality of recesses of the first pivot member and on the one of the plurality of recesses of the second pivot member, respectively.Type: GrantFiled: February 7, 2014Date of Patent: December 29, 2015Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Yen-Cheng Lin, Hsin-Liang Chen
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Patent number: 9196610Abstract: A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.Type: GrantFiled: May 13, 2014Date of Patent: November 24, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing-Chor Chan, Hsin-Liang Chen
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Publication number: 20150333052Abstract: A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Applicant: Macronix International Co., Ltd.Inventors: Wing-Chor Chan, Hsin-Liang Chen
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Publication number: 20150325570Abstract: A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: Macronix Internatioanl Co., Ltd.Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
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Publication number: 20150179754Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.Type: ApplicationFiled: March 9, 2015Publication date: June 25, 2015Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 9054524Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.Type: GrantFiled: October 19, 2012Date of Patent: June 9, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsin-Liang Chen, Shuo-Lun Tu
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Patent number: 9029976Abstract: Provided is a semiconductor device which increases a concentration around an emitter by arranging a lightly doped region (HNMLDD). When the semiconductor device is operated in a forward bias, a maximum common-emitter current gain is obtained in a forward-active region, such that signals are amplified and an unnecessary noise is decreased at the same time. Further, the semiconductor device of the invention further includes a field plate disposed on a substrate between the emitter and a base or/and the collector and the base, and configured to change a potential distribution of junctions between each of doped regions and raise a breakdown voltage of the junctions.Type: GrantFiled: December 27, 2013Date of Patent: May 12, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 9029952Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.Type: GrantFiled: April 19, 2012Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20150098195Abstract: A foldable assembly includes a first plate component, a second plate component and a pivot assembly. The pivot assembly comprises a first pivot member, a second pivot member and a third pivot member. The first pivot member and the second pivot member are connected with the first plate component and the second plate component, respectively. Each of the first pivot member and the second pivot member has an axial hole and a plurality of recesses. Each of the two opposite sides of the third pivot member has a shaft and a protrusion located on an outer wall surface of the shaft. The two shafts are adapted for being rotatable on the two axial holes, respectively. The two protrusions are located on one of the plurality of recesses of the first pivot member and on the one of the plurality of recesses of the second pivot member, respectively.Type: ApplicationFiled: February 7, 2014Publication date: April 9, 2015Applicants: INVENTEC CORPORATION, Inventec (Pudong) Technology CorporationInventors: Yen-Cheng LIN, Hsin-Liang CHEN
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Patent number: 8963253Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.Type: GrantFiled: October 23, 2012Date of Patent: February 24, 2015Assignee: Macronix International Co., Ltd.Inventors: Hsin-Liang Chen, Shuo-Lun Tu
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Publication number: 20150048415Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20140375207Abstract: A large-area plasma generating apparatus is disclosed, which includes a reaction chamber; a first electrode disposed in the reaction chamber; a second electrode parallel with the first electrode and disposed in the reaction chamber; and a discharge region formed between the first and second electrodes and a plasma can be formed therein; wherein a travelling wave or a traveling-wave-like electromagnetic field is generated via at least one of the first and second electrodes and travels from one end of the discharge region to its opposite end, so as to uniform the plasma in the discharge region.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: HSIN-LIANG CHEN, CHENG-CHANG HSIEH, DENG-LAIN LIN, YAN-ZHENG DU, CHI-FONG AI, MING-CHUNG YANG
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Patent number: 8908369Abstract: A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets.Type: GrantFiled: March 5, 2013Date of Patent: December 9, 2014Assignees: Inventec (Pudong) Technology Corporation, Inventec CorporationInventors: Yen-Cheng Lin, Ming-Hung Shih, Hsin-Liang Chen
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Patent number: 8878241Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.Type: GrantFiled: December 18, 2013Date of Patent: November 4, 2014Assignee: Macronix International Co., Ltd.Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu