Abstract: A quantum computer and a method for generating an ansatz circuit are provided. The method includes: defining, by a processor, a scattering matrix according to an interacting term of a Hamiltonian function based on Gellman-Low theorem; generating, by the processor, a variational form of the scattering matrix; generating, by the processor and a quantum processor, an operator of the ansatz circuit according to the variational form; and performing, by the quantum processor, a quantum operation according to the operator to process input data.

Abstract: Anion antisite defects in monolayer Transition Metal Dichalcogenide (TMD) systems are here identified as two-dimen-sional solid-state defect qubits. The proposed antisites in these TMDs host paramagnetic triplet ground states with flexible level splitting. A viable transition loop between the triplet and singlet defect states is demonstrated, including optical excitations/relaxations and nonradiative decay paths for the antisites as qubits. A complete set of qubit operational processes, including initialization, manipulation, and readout, is delineated.

Abstract: An electrically controlled nanomagnet and a spin orbit torque magnetic random access memory (SOT-MRAM) including the same are provided. The electrically controlled nanomagnet includes: a first spin-Hall material layer including a first spin-Hall material; a second spin-Hall material layer including a second spin-Hall material; and a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer, wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.

Abstract: An electrically controlled nanomagnet and a spin orbit torque magnetic random access memory (SOT-MRAM) including the same are provided. The electrically controlled nanomagnet includes: a first spin-Hall material layer including a first spin-Hall material; a second spin-Hall material layer including a second spin-Hall material; and a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer, wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.

Abstract: Transition metal dichalcogenide (TMD)-based spintronics devices, each including a TMD thin film layer, a first gate electrode, a first insulating layer sandwiched between the TMD thin film layer and the first gate electrode, a second gate electrode, and a second insulating layer sandwiched between the TMD thin film layer and the second gate electrode. Such a device, when also including a source electrode and a drain electrode, functions as a spin filter. On the other hand, when also including one source electrode and two drain electrode terminals, such a device functions as a spin separator. Also disclosed are methods of using the above-described TMD-based spintronics devices.

Abstract: Provided in one embodiment is a device, comprising: a substrate; and a layer disposed over the substrate, wherein the layer comprises a monolayer of crystals comprising a Group IV element.

Abstract: Provided in one embodiment is a device, comprising: a substrate; and a layer disposed over the substrate, wherein the layer comprises a monolayer of crystals comprising a Group IV element.

Abstract: A computer-implemented method for content endorsement includes receiving, at a server, postings from posters; receiving, for each posting, a posting fee; receiving endorsements drawn by the postings; receiving, for each endorsement, an endorsement fee; collecting the endorsement fees into a pot; based on the endorsements, defining a subset of postings; and allocating at least a portion of the pot to postings in the subset of postings.

Abstract: Rotary mechanisms are provided. A rotary mechanism comprises a first member, a second member rotatable with respect to the first member along a first axis, and a first washer fixed to the first member. The first washer comprises a plurality of protrusions projecting toward the second member. The second washer is fixed to the second member and comprises a plurality of sliding surfaces, a plurality of depressions respectively disposed between the sliding surfaces, and a plurality of openings formed on the sliding surfaces. The protrusions are joined in the openings when the second member rotates to an angle with respect to the first member.

Abstract: The present invention provides a high-speed low-voltage programming scheme and self-convergent high-speed low-voltage erasing schemes for Electrically Erasable Programmable Read-Only Memories (EEPROM). For the N-type Field Effect Transistor (NFET) based NVM programming, an elevated source voltage to the substrate can achieve high efficient Drain-Avalanche-Hot-Electron Injection (DAHEI) into the floating gate resulting in high-speed and low-voltage operations. The self-convergent and low-voltage erasing can be achieved by applying Drain-Avalanche-Hot Hole Injection (DAHHI) with the conditions of restricted maximum drain current and a moderate control gate voltage enough to turn on the NFET. For the p-type FET (PFET) based EEPROM programming, a negative source voltage relative to the substrate can achieve high efficient Drain-Avalanche-Hot-Hole Injection (DAHHI) into the floating gate resulting in high-speed and low voltage operations.

Abstract: Methods of treating diabetes in mammals, particularly humans, by blocking or inhibiting VEGF-mediated activity. A preferred inhibitor of VEGF-mediated activity is a VEGF antagonist such as the VEGF fusion protein trap of SEQ ID NO:2 capable of binding and blocking VEGF. The method of the invention may be combined with other therapies, such as with insulin therapy.

Abstract: A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a semiconductor substrate. The transistor comprises a first conducting gate stacked on the surface of a dielectric with doped regions formed at two sides thereof as a source and a drain. The capacitor comprises a doped region, a dielectric stacked thereon, and a second conducting gate. The conducting gates of the capacitor and the transistor are electrically connected together to form a single floating gate of the memory cell. The semiconductor substrate is p-type or n-type. Besides, a back-bias program write-in and related erase and readout operation ways are proposed for the single-gate memory cells.