Patents by Inventor Hsin Lin WU

Hsin Lin WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063778
    Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng, Chi On Chui, Kun-Yu Lee, Tzer-Min Shen, Yen-Tien Tung, Chun-I Wu
  • Patent number: 12230534
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Publication number: 20230383399
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Publication number: 20220275500
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Patent number: 11174157
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
  • Patent number: 11081413
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 3, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin Lin Wu, Yu-Hsuan Tsai, Chang Chin Tsai, Lu-Ming Lai, Ching-Han Huang
  • Publication number: 20200002162
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Hsuan TSAI, Yin-Hao CHEN, Hsin Lin WU, San-Kuei YU
  • Publication number: 20190267298
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin Lin WU, Yu-Hsuan TSAI, Chang Chin TSAI, Lu-Ming LAI, Ching-Han HUANG