Abstract: A package structure includes: a substrate includes a first surface; a semiconductor chip disposed on the first surface; a support disposed on the first surface and surrounding the semiconductor chip comprises an electrical conducting member and penetrating the support; and an optical component disposed on the support and electrically connected to the substrate by the electrical conducting member.

Abstract: An apparatus for producing silicon carbide crystal is provided and includes a composite structure formed by a plurality of graphite layers and silicon carbide seed crystals, wherein a density or thickness of each layer of graphite is gradually adjusted to reduce a difference of a thermal expansion coefficient and Young's modulus between the graphite layers and silicon carbide. The composite structure can be stabilized on a top portion or an upper cover of a crucible made of graphite, thereby preventing the silicon carbide crystal from falling off.

Abstract: The present disclosure relates to an apparatus and a method of delivering a liquid to a downstream process. The apparatus can include a vessel configured to retain a liquid, a bellow in fluid communication with the vessel to receive the liquid from the vessel and in fluid communication with the downstream process to deliver the liquid. The bellow can be exposed to a constant external pressure and configured to deliver the liquid under the constant external pressure when the bellow stops receiving the liquid from the vessel. In some embodiments, the constant external pressure is atmospheric pressure. The bellow can include a pressure deformable material. The apparatus can further include a vaporizer configured to receive the liquid and to produce a vapor, one or more chemical vapor deposition chambers configured to receive the vapor and to hold a substrate for deposition of a component of the vapor on a substrate.

Abstract: The present disclosure relates to an apparatus and a method of delivering a liquid to a downstream process. The apparatus can include a vessel configured to retain a liquid, a bellow in fluid communication with the vessel to receive the liquid from the vessel and in fluid communication with the downstream process to deliver the liquid. The bellow can be exposed to a constant external pressure and configured to deliver the liquid under the constant external pressure when the bellow stops receiving the liquid from the vessel. In some embodiments, the constant external pressure is atmospheric pressure. The bellow can include a pressure deformable material. The apparatus can further include a vaporizer configured to receive the liquid and to produce a vapor, one or more chemical vapor deposition chambers configured to receive the vapor and to hold a substrate for deposition of a component of the vapor on a substrate.

Abstract: A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Abstract: A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Abstract: A digital video disc (DVD) recording device including an interface for communicating between the DVD recording device and a host, an error detection code (EDC) generator receiving data sent directly from the interface and generating a data frame by adding an EDC to the data, and a scrambler for scrambling the data frame sent directly from the EDC generator.

Abstract: A system for error correction that comprises a servo device receiving data sent from an optical pickup head and determining whether the data include a first error, a read channel determining whether the data include a second error, a demodulator determining whether the data include a third error, and a controller marking the data with a flag if it is determined that the data include the first, second, or third error.

Abstract: A programmable frequency following device is provided. The programmable frequency following device includes a frequency divider for dividing the input frequency by a predetermined divisor. A frequency counter is used to count the output frequency of the programmable frequency following device, the frequency counter being reset to 0 after reaching a cycle time of the output frequency from the frequency divider. A programmable frequency comparator is used to compare the output count from the frequency counter with a user-programmable reference value at the time before the frequency counter is reset to 0. An up-down counter is under control by the programmable frequency comparator to count either in the upward or downward direction, and the count is locked when the output frequency reaches an intended value.

Abstract: A method and apparatus processing a Reed-Solomon Product-like Code (RSPC) error correction in a substantially real time mode are provided. Two RSPC error correctors are provided in the CD-ROM decoder which perform RSPC error correction over the LSB and MSB of each word respectively. In addition, a 16-bit buffer-memory or a Fast-Page-Mode buffer-memory is provided to store the CD-ROM data temporarily. The LSB and MSB of each word are retrieved from the buffer memory during the same memory cycle and fed to the first and second RSPC error corrector substantially at the same time. The first RSPC error corrector performs the RSPC operation over the LSB. The second RSPC error corrector performs the RSPC operation over the MSB. The respective operations are performed during substantially the same time interval. The invention results in shorter buffer-memory access time and shorter overall RSPC processing time and achieves a substantially real time access of a high speed CD-ROM.