Abstract: An acoustic scene conversion method, comprising: receiving sound signals including user's speech and scenic sounds; processing the sound signals according to an artificial intelligence model to generate enhanced speech signals without scenic sounds; and mixing the enhanced speech signals with new scenic sounds to produce converted sound signals.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: An acoustic scene conversion method, comprising: receiving sound signals including user's speech and scenic sounds; processing the sound signals according to an artificial intelligence model to generate enhanced speech signals without scenic sounds; and mixing the enhanced speech signals with new scenic sounds to produce converted sound signals.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: A method for diagnosis of diseases adopted on an electronic stethoscope which includes at least two sound receiving portions, a noise control portion, a processing portion, a data portion and an output portion. The method includes: first, the sound receiving portions receive sound signals issued from a patient's lungs included external noises; next, the sound signals are sent to the noise control portion which eliminates the external noise, and the processing portion to be overlapped and intensified; then characteristic values are retrieved from the sound signals to be compared with disease sound signal data in the data portion; finally the output portion outputs a diseases judgment result. Thus the electronic stethoscope can perform automatic interpretation of diseases to reduce human erroneous diagnostic judgment. Users also can get preliminary understanding of their body conditions when doctors are absent.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.

Abstract: An apparatus and method for clock adjustment in a receiving end of a communication system. The receiving end includes an analog to digital converter (ADC) and a frequency/phase error estimator. The ADC receives a transmitting signal and converts to a digital signal. The frequency/phase error estimator receives the digital signal and accordingly outputs a phase error signal. The device for clock adjustment includes a shaping filter and a phase adjuster. The shaping filter outputs a phase adjustment signal in accordance with the phase error signal and has a noise shaping property. The phase adjuster is connected to the shaping filter for outputting a clock signal in accordance with the phase adjustment signal.

Abstract: The present invention provides sequential feedback Header Error Correction (HEC) checking method and circuit for Asynchronous Transfer Mode (ATM). With design of hardware circuit, the present invention of sequential feedback Header Error Correction (HEC) checking method and circuit will allocate the cell boundary in ATM communication, and meanwhile control the state switching among three operation for cell delineation logic, i.e., HUNT, PRESYNC and SYNC.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.