Patents by Inventor Hsin-Ming Chen

Hsin-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310544
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Patent number: 11437280
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20220269467
    Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.
    Type: Application
    Filed: January 10, 2022
    Publication date: August 25, 2022
    Applicant: QISDA CORPORATION
    Inventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
  • Publication number: 20220260926
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20220238693
    Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Publication number: 20220238632
    Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Kuo-Chih Lai, Chi-Mao Hsu, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Hsin-Fu Huang
  • Publication number: 20220223727
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 14, 2022
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20220221147
    Abstract: A burner of a gas stove includes a burner body, a partition member, and at least one flame cover. The burner body includes a gas conduit and a base. The gas conduit has at least one gas input passage for injecting gas and air, and the base has at least one mixture passage for mixing the gas and the air. The at least one mixture passage communicates with the at least one gas input passage. The partition member has a plurality of through holes and covers the at least one mixture passage. The at least one flame cover provided with a plurality of flame holes covers the partition member. Whereby, the size of the burner of the gas stove is reduced significantly, and the gas can mix with the air effectively and uniformly.
    Type: Application
    Filed: March 10, 2022
    Publication date: July 14, 2022
    Applicant: GRAND MATE CO., LTD.
    Inventors: CHUNG-CHIN HUANG, Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh, Wei-Long Chen, Kuan-Chou Lin, Tang-Yuan Luo
  • Patent number: 11373971
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Patent number: 11374107
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 11372216
    Abstract: An imaging optical lens system includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element has negative refractive power. The second lens element has an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof. The third lens element has positive refractive power. The fourth lens element has positive refractive power. The fifth lens element has negative refractive power. The sixth lens element has positive refractive power. The imaging optical lens system has a total of six lens elements.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 28, 2022
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ming Chen, Yu-Tai Tseng, Hsin-Hsuan Huang, Shu-Yun Yang
  • Publication number: 20210234264
    Abstract: Radio devices for wireless transmission including an integrated adjustable mount allowing mounting to a pole or stand and adjustment of the angle of the device (e.g., the altitude). The device may include a compact array antenna having a high gain configured to operate in, for example, the 5.15 to 5.85 GHz band and/or the 2.40-2.48 GHz band. The antenna emitters may be arranged in a separate plane from a plane containing the antenna feed connecting the emitting elements and also from a ground plane. The antenna array may be contained within a protective weatherproof housing along with the radio control circuitry.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Gerardo HUERTA, Jude LEE, Hsin-Ming CHEN, Robert PERA
  • Patent number: 11070383
    Abstract: A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 20, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 11057223
    Abstract: The communication system includes a communication buffer and a communication terminal. The communication buffer includes a physical unclonable function (PUF) device, and the communication buffer provides a security key generated by the PUF device. The communication terminal is coupled to the communication buffer, and transmits a mapping request to the communication buffer to ask for the security key. The communication terminal manipulates the transmission data with the security key to generate the encrypted data, and transmits the encrypted data to the communication buffer. The communication buffer further restores the transmission data from the encrypted data according to the security key.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 6, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 11050575
    Abstract: An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 29, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Chih-Min Wang, Hsin-Ming Chen
  • Patent number: 11011835
    Abstract: Radio devices for wireless transmission including an integrated adjustable mount allowing mounting to a pole or stand and adjustment of the angle of the device (e.g., the altitude). The device may include a compact array antenna having a high gain configured to operate in, for example, the 5.15 to 5.85 GHz band and/or the 2.40-2.48 GHz band. The antenna emitters may be arranged in a separate plane from a plane containing the antenna feed connecting the emitting elements and also from a ground plane. The antenna array may be contained within a protective weatherproof housing along with the radio control circuitry.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: May 18, 2021
    Assignee: UBIQUITI INC.
    Inventors: Gerardo Huerta, Jude Lee, Hsin-Ming Chen, Robert Pera
  • Publication number: 20210047866
    Abstract: Locking mechanisms are described herein. In one example, a locking mechanism can include an aperture to receive a lock head when the lock head is in a first position, a latch head to prevent the lock head from moving through the aperture when the lock head is in a second position, and/or an actuator coupled to the latch head to move the lock head from the second position to the first position in response to an authentication.
    Type: Application
    Filed: April 19, 2018
    Publication date: February 18, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventor: Hsin-Ming Chen
  • Patent number: 10915464
    Abstract: A security system includes a physical unclonable function circuit, a write-in protection circuit, a memory, and a readout decryption circuit. The physical unclonable function circuit provides a plurality of random bit strings. The write-in protection circuit receives a write-in address and original data, and includes an address scrambling unit. The address scrambling unit generates a scrambled address by scrambling a write-in address according to a random bit string provided by the physical unclonable function circuit. The memory stores the storage data corresponding to the original data according to the scrambled address. The readout decryption circuit reads out the storage data from the memory according to the write-in address to derive the original data.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 9, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
  • Patent number: 10691414
    Abstract: A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 23, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 10649735
    Abstract: A security system with entropy bits includes a physically unclonable function circuit, and a security key generator. The physically unclonable function circuit provides a plurality of entropy bit strings. The security key generator generates a security key by manipulating a manipulation bit string derived from the plurality of entropy bit strings according to an operation entropy bit string. Each bit of the operation entropy bit string is used to determine whether to perform a corresponding operation to the manipulation bit string.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 12, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang