Patents by Inventor Hsin Pang

Hsin Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11294577
    Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
  • Publication number: 20210263656
    Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.
    Type: Application
    Filed: March 26, 2020
    Publication date: August 26, 2021
    Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
  • Publication number: 20210161788
    Abstract: The present disclosure provides an anti-blue light dermal topical composition which comprises terephthalylidene dicamphor sulfonic acid as an ingredient for effective anti-blue light and further rutoside for a better anti-blue light effect; the dermal topical composition contributes to skin health care and moderate skin damages attributed to blue light in environment; the present disclosure also provides an application of terephthalylidene dicamphor sulfonic acid to preparation of an anti-blue light medicament composition.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 3, 2021
    Inventors: Chen-I Pang, Wen-Hsin Pang, Ya-Ching Tsui, Shu-Fen Li, Chi-Chun Pan
  • Publication number: 20200365769
    Abstract: A semiconductor device is provided, which includes a base, a semiconductor structure and a conductive reflective structure. The base has a first surface and a second surface opposite to the first surface. The semiconductor structure is located on the first surface. The conductive reflective structure is located on the second surface and includes a metal oxide structure and a metal structure. The metal oxide structure is located between the metal structure and the base. The metal oxide structure physically contacts the second surface.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Inventors: Yao-Ru CHANG, Wen-Luh LIAO, Yung-Fu CHANG, Hsiang CHANG, Meng-Yang CHEN, Yun-Hsin PANG, Yi HSIAO
  • Patent number: 10580499
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 3, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
  • Patent number: 10352986
    Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Pang Lu, Hsin-Wen Chen
  • Publication number: 20190043587
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 7, 2019
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
  • Publication number: 20170345720
    Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.
    Type: Application
    Filed: May 25, 2016
    Publication date: November 30, 2017
    Inventors: Hsin-Pang Lu, Hsin-Wen Chen
  • Patent number: 9566642
    Abstract: A composite core die includes a reusable core die; and a disposable core die. The disposable core die is in physical communication with the reusable core die and surfaces of communication between the disposable core die and the reusable core die serve as barriers to prevent the leakage of a slurry that is disposed in the composite core die.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 14, 2017
    Assignee: General Electric Company
    Inventors: Ching-Pang Lee, Hsin-Pang Wang, Ram Kumar Upadhyay, Paul Richard Myers, Marc Thomas Edgar, Thomas Donald Martyn, Eric Alan Estill
  • Patent number: 9492968
    Abstract: A system and a method of fabricating a complex three dimensional part are described. The system comprises a rapid prototyping machine configured to provide a disposable mold having a negative imprint of a complex three dimensional structure, a mixer, an injection molding machine, and a furnace system. A slurry comprising a powder and a binder is introduced into the disposable mold, the binder is cured, the disposable mold is removed, and the binder is removed, leaving an intact cured structure. The cured structure is sintered to fabricate the complex three dimensional part.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: November 15, 2016
    Assignee: General Electric Company
    Inventors: Hsin-Pang Wang, Erin Marie Perry
  • Patent number: 9263134
    Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
  • Publication number: 20150262621
    Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
  • Patent number: 9093131
    Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 28, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsi-Wen Chen, Hsin-Pang Lu
  • Publication number: 20150170718
    Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsi-Wen Chen, Hsin-Pang Lu
  • Publication number: 20150095728
    Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Pang Lu, Hsi-Wen Chen, Ya-Nan Mou, Chung-Cheng Tsai, Hsiao-Chieh Sung, Yin-Ju Hsiao
  • Publication number: 20140376316
    Abstract: A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided.
    Type: Application
    Filed: June 23, 2013
    Publication date: December 25, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shi-Wen CHEN, Hsin-Pang Lu
  • Patent number: 8884182
    Abstract: A method of modifying an end wall contour is provided. The method includes creating a weld pool using a laser, adding a metal or a ceramic powder or a wire filler to the melt pool and modifying the part of the turbine in a manner that results in a change of about 0.005 to about 50 volume percent in the part of the turbine. The weld pool is created on a turbine component and contains molten metal or ceramic derived as a result of a heat interaction between the laser and the turbine component.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: November 11, 2014
    Assignee: General Electric Company
    Inventors: Ching-Pang Lee, Hsin-Pang Wang, Ronald Scott Bunker, Sudhir Kumar Tewari, Magdi Naim Azer
  • Patent number: 8804440
    Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Shi-Wen Chen, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
  • Publication number: 20140211573
    Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 31, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shi-Wen CHEN, Hsin-Pang LU, Chung-Cheng TSAI, Ya-Nan MOU
  • Publication number: 20140204686
    Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 24, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shi-Wen CHEN, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou