Abstract: A light source device includes a light guide plate, an optical adhesive, and a light source element. The light guide plate includes a light guide substrate and an enhancement layer. The light guide substrate has a light incident surface, a first surface, and a second surface. The first surface is opposite to the second surface, and the light incident surface extends between the first surface and the second surface. The enhancement layer is disposed on the light guide substrate. A thickness of the enhancement layer is from 1 micrometer to 25 micrometers and a first refractive index of the light guide substrate is greater than a second refractive index of the enhancement layer. The optical adhesive is interposed between the first surface of the light guide substrate and the optical adhesive. The light source element is disposed beside the light incident surface to emit light toward the light incident surface.

Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: A guard ring structure includes: a bottom metal layer; a protection structure located on the bottom metal layer, wherein the protection structure includes an insertion portion, an interconnection portion, and a metal layer stacked in sequence from bottom to top, and the insertion portion is inserted into the nearest underlining metal layer under the interconnection.

Abstract: Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening.

Abstract: The present application discloses a graphic element structure and a graphic array structure. The graphic element structure includes a first graphic, a second graphic, and a third graphic, where the first graphic includes a first part and a second part that are perpendicular to each other, and a tail end of the first part of the first graphic is connected to a head end of the second part of the first graphic; orthographic projection of a first interconnection structure on the first graphic is located in the second part of the first graphic; the second graphic includes a first part and a second part that are perpendicular to each other; orthographic projection of a second interconnection structure on the second graphic is located in the second part of the second graphic; and the third graphic is located between the first graphic and the second graphic.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The method includes: forming a laminated structure, wherein the laminated structure includes first dielectric layers and second dielectric layers laminated alternately and sequentially from bottom to top; forming a contact hole, wherein the contact hole penetrates the laminated structure at least in a thickness direction, and a width of a part, of the contact hole, in the second dielectric layer is greater than a width of a part, of the contact hole, in the adjacent first dielectric layer; and forming contact structure in the contact hole, wherein the contact structure fills up the contact hole.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, a bottom protecting wall being formed in the substrate; forming a mask layer on the substrate; forming a groove in the mask layer, a non-zero angle existing between a sidewall of the groove and a sidewall of the bottom protecting wall, and the bottom of the groove extending into the substrate; and forming a top protecting wall in the groove, the top protecting wall being in direct contact with the bottom protecting wall.

Abstract: The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure comprises: a substrate, in which a first protective structure is formed, is provided; a first dielectric layer is formed on the substrate; and a second protective structure is formed in the first dielectric layer and the substrate. A projection of the second protective structure and a projection of the first protective structure in a direction perpendicular to a surface of the substrate are at least partially overlapped, and there is a spacing between a projection of the second protective structure and a projection of the first protective structure in a direction along the surface of the substrate.

Abstract: A semiconductor structure includes a chip structure and a sealing structure disposed on a substrate of the semiconductor structure. The sealing structure includes a metal wall body and a blocking wall body located on a top of the metal wall body, and the metal wall body and the blocking wall body both are disposed around the chip structure.

Abstract: A manufacturing method of a semiconductor structure includes: a substrate is provided; and an intermediate layer is formed on the substrate, an I-shaped member and a wall-shaped member are formed in the intermediate layer, a top surface of the wall-shaped member is not lower than a top surface of the I-shaped member, and a bottom surface of the wall-shaped member is not higher than a bottom surface of the I-shaped member.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, the substrate including an array area and a metal interconnection area located at the periphery of the array area; and forming a metal interconnection structure in the metal interconnection area, in which the metal interconnection structure includes a plurality of stacked metal wiring layers and a plurality of connecting pillars connected between each of the metal wiring layers, each of the metal wiring layer includes a plurality of metal strips distributed at intervals, the metal strips of two adjacent metal wiring layers are staggered, and two adjacent metal strips located in a same layer are respectively connected with one same metal strip directly below them through the connecting pillars.

Abstract: Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening.

Abstract: Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate; an integrated circuit region formed in the semiconductor substrate; and a seal ring arranged in the semiconductor substrate and around the integrated circuit region and configured to protect the integrated circuit region, wherein the seal ring has a wavy structure.

Abstract: The present application discloses a fuse structure and a formation method. The fuse structure includes: a first dielectric layer, and at least two discrete first conductive plugs penetrating the first dielectric layer; a second conductive plug, the second conductive plug being electrically connected to the at least two first conductive plugs; a top metal layer, the top metal layer being electrically connected to the second conductive plug, and located on one side of the second conductive plug which is far from the first conductive plugs; and a second dielectric layer, the second dielectric layer being located on the top of the first dielectric layer, and the second conductive plug and the top metal layer being located in the second dielectric layer. The embodiments of the present application simplify the fuse structure, increasing the output efficiency of the fuse structure.

Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

Abstract: A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being in direct contact with the second cell contact region.