Abstract: An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.

Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.

Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.

Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.

Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.