Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.

Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.

Abstract: A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.

Abstract: A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.

Abstract: Disclosed herein is a method of forming a low-k layer. The method includes the following steps. Tetraalkoxysilane, ethanol, tetraalkylammonium hydroxide and water are mixed in a molar ratio between 1:0.1:0.1:5 and 1:10:0.5:36 to form a first mixture. The first mixture is heated for a period of less than about 36 hours to form a second mixture containing a plurality of non-crystalline silicon-containing particles, wherein each of the non-crystalline silicon-containing particles has a particle size of smaller than about 10 nm. Subsequently, a surfactant is added to the second mixture to form a colloid solution, in which the surfactant has a concentration of about 1-20% by weight of the colloid solution. The colloid solution is coated on a substrate and thereby forming a colloid layer thereon. Then, the colloid layer is heated at a condition sufficient to transform the colloid layer into the low-k layer.

Abstract: Discloses herein is a method of forming a low-k layer. The method includes the following steps. Tetraalkoxysilane, ethanol, tetraalkylammonium hydroxide and water are mixed in a molar ratio between 1:0.1:0.1:5 and 1:10:0.5:36 to form a first mixture. The first mixture is heated for a period of less than about 36 hours to form a second mixture containing a plurality of non-crystalline silicon-containing particles, wherein each of the non-crystalline silicon-containing particles has a particle size of smaller than about 10 nm. Subsequently, a surfactant is added to the second mixture to form a colloid solution, in which the surfactant has a concentration of about 1-20% by weight of the colloid solution. The colloid solution is coated on a substrate and thereby forming a colloid layer thereon. Then, the colloid layer is heated at a condition sufficient to transform the colloid layer into the low-k layer.

Abstract: Discloses herein is a method of forming a low-k layer. The method includes the following steps. Tetraalkoxysilane, ethanol, tetraalkylammonium hydroxide and water are mixed in a molar ratio between 1:0.1:0.1:5 and 1:10:0.5:36 to form a first mixture. The first mixture is heated for a period of less than about 36 hours to form a second mixture containing a plurality of non-crystalline silicon-containing particles, wherein each of the non-crystalline silicon-containing particles has a particle size of smaller than about 10 nm. Subsequently, a surfactant is added to the second mixture to form a colloid solution, in which the surfactant has a concentration of about 1-20% by weight of the colloid solution. The colloid solution is coated on a substrate and thereby forming a colloid layer thereon. Then, the colloid layer is heated at a condition sufficient to transform the colloid layer into the low-k layer.