Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element has two surfaces being both aspheric. The fourth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, wherein two surfaces thereof are aspheric. The fifth lens element has an image-side surface being convex in a paraxial region thereof, wherein two surfaces thereof are aspheric.

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

Abstract: A light source module and a display device are provided. The light source module includes a light source, a light guide plate, and an optical film set including multiple first optical microstructures having a first surface, multiple second optical microstructures having a second surface, and multiple third optical microstructures having a third surface. Each of the multiple first optical microstructures has a first vertex angle, each of the multiple second optical microstructures has a second vertex angle, and each of the multiple third optical microstructures has a third vertex angle. The third vertex angle is less than the first vertex angle, and the first vertex angle is less than or equal to the second vertex angle. By configuring the aforementioned optical microstructures, the light source module of the disclosure may greatly improve the collimation of light and has favorable luminance.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element has two surfaces being both aspheric. The fourth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, wherein two surfaces thereof are aspheric. The fifth lens element has an image-side surface being convex in a paraxial region thereof, wherein two surfaces thereof are aspheric.

Abstract: An electronic device includes a first component and a second component. The first component includes a first housing and a protrusion element. The first housing has a first cover plate, and the protrusion element is disposed on the first cover plate. The second component is rotationally assembled with the first component along a first direction. The second component includes a second housing, an elastic structure, and a switching element. The elastic structure has an elastic post. The second housing has a second cover plate having a through hole. One part of the elastic post passes through the through hole and is exposed on the second cover plate. The protrusion element moves along a first direction relative to the elastic structure, such that the elastic post is squeezed by the protrusion element to move along a second direction and presses the switching element.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: An optical module includes a micro spectrometer. The micro spectrometer includes an optical crystal, a lens, and a photosensitive assembly. The optical crystal is configured to receive detection light and covert the detection light into interference light. The optical crystal is surrounded by a sleeve, the sleeve configured to fix a position of the optical crystal. The lens is configured for receiving the interference light and focusing the interference light. The photosensitive assembly is configured for imaging the interference light into an interference image. The optical module further comprises a controller. The controller is electrically connected to the photosensitive assembly, and the controller is used to convert the interference image into light wavelength signals and light intensity signals.

Abstract: A port replicator is applicable to an electronic device having one or more connecting port and includes a shell including an abutting portion and an extending portion connected with each other and a replicating circuit module. The insides of the abutting portion and the extending portion communicate with each other to form a receiving space. The abutting portion includes at least a downstream opening disposed at the front end of the abutting portion, one or more upstream openings disposed at the rear end of the extending portion, and a positioning slot disposed at the upper end of the abutting portion. The replicating module is assembled in the receiving space and includes at least one downstream port disposed corresponding to the downstream opening and one or more upstream port passing through the upstream opening and extended out of the shell.