Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.

Abstract: A backlight module configured to illuminate at least one key cap of a lighting keyboard. The backlight module comprises a lighting board, a light emitting unit and a light guide plate. The lighting board has a first reflective layer, a lighting circuit and two aligned micro-structure regions, all three at least partially being layered in parallel with each other. The two micro-structure regions reflect lights and are separated by the lighting circuit. The light emitting unit includes plural color dies connecting electrically with the lighting circuit. The light guide plate has a light guide hole for accommodating the light emitting unit. The color dies of the light emitting unit are aligned linearly, while the two micro-structure regions of the lighting board are aligned in perpendicular to the linearly-aligned color dies, with the micro-structure regions disposed at opposite sides the light emitting unit.

Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.

Abstract: A memory array and structure are provided. The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A memory array and structure are provided The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.

Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.

Abstract: A memory apparatus and a data access method for a memory are provided. The data access method includes: receiving a data erase command for performing a data erase operation; and, during the data erase operation: configuring a selected memory cell block in the memory according to the data erase command; providing a flag memory cell corresponding to the selected memory cell block, erasing a data in the flag memory cell according to the data erase command, and keeping a data in a plurality of selected memory cells in the selected memory cell block unchanged.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: An integrated circuit includes a three-dimensional cross point memory array having M levels of memory cells disposed in cross points of N first access line layers and P second access line layers. The integrated circuit further comprises first and second sets of first access line drivers. The first set of first access line drivers is operatively coupled to apply a common first operational voltage to selected first access lines in odd first access line layers. The second set of first access line drivers is operatively coupled to apply the common first operational voltage to selected first access lines in even first access layers. A plurality of sets of second access line drivers is operatively configured to apply a second operational voltage to selected second access lines in selected second access line layers.

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

Abstract: Devices are provided for measuring and/or adjusting the distance between two opposing surfaces of a work space, such as two vertebral bodies separated by a disc space. A sizing device may include at least one distraction member, an actuator, and an actuator controller. The actuator controller is movable to move the actuator, with movement of the actuator changing the height dimension of the distraction member. The amount of movement of the actuator controller is generally linearly related to the change of the height dimension of the distraction member throughout the entire range of motion of the actuator controller. The amount of expansion force applied by the distraction member is also generally linearly related to the amount of movement of the actuator controller.

Abstract: A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.

Abstract: A memory device includes an array of programmable resistance memory cells, a differential amplifier coupled to the array, and current circuitry providing a program current to the bit line. The differential amplifier senses a voltage difference between a first voltage on a bit line coupled to a memory cell and a reference voltage, and provides a feedback signal in response to the voltage difference. Control circuitry is coupled to the array and the differential amplifier, and configured to execute a program operation to change the memory cell in a first resistance state to a second resistance state, including selecting a voltage level for the reference voltage which correlates with the second resistance state, turning on the current circuitry to apply a program pulse of program current to the memory cell, and enabling the differential amplifier, where the current circuitry turns off the program current in response to the feedback signal.

Abstract: A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.

Abstract: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state.