Abstract: An illuminating circuit structure includes a film sheet, an illuminant, a printed baseline layer, and a printed pad layer. The printed baseline layer includes a first baseline segment and a second baseline segment printed on the film sheet, while the printed pad layer includes a first bar pad and a second bar pad. For a first baseline head of the first baseline layer and a first pad head of the first bar pad, one of which extends along a first direction and the other of which extends along a second direction not parallel to the first direction. Therefore, the first baseline segment and the first bar pad achieve electrical connection despite of an existed print shifting. Similarly, a second baseline head of the second baseline layer and a second pad head of the second bar pad also can achieve electrical connection despite of an existed print shifting.

Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.

Abstract: An illuminated touchpad includes a panel, a light guide layer and a circuit board. The panel includes a first light transmitting region and a second light transmitting region. The light guide layer includes a first light guide region and a second light guide region. The circuit board includes a controller, a touch module, a first light source and a second light source. The controller controls the first light source to emit light, such that the first light guide region guides the light emitted by the first light source to the first light transmitting region. When the touch module senses that the first light transmitting region is touched, the controller controls the second light source to emit light, such that the second light guide region guides the light emitted by the second light source to the second light transmitting region.

Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.

Abstract: Polyvinyl alcohol (PVA) gel and polyurethane (PU)ZPVA gel and gel beads, methods for making gel and gel beads with immobilized substances such as microorganisms, cells, enzymes, and/or other materials, methods for using gel and gel beads in various applications (e.g., wastewater treatment), and apparatus for manufacturing such gel and gel beads, are described.

Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.

Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.

Abstract: A memory array and structure are provided. The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A memory array and structure are provided The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.

Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.

Abstract: A memory apparatus and a data access method for a memory are provided. The data access method includes: receiving a data erase command for performing a data erase operation; and, during the data erase operation: configuring a selected memory cell block in the memory according to the data erase command; providing a flag memory cell corresponding to the selected memory cell block, erasing a data in the flag memory cell according to the data erase command, and keeping a data in a plurality of selected memory cells in the selected memory cell block unchanged.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: An integrated circuit includes a three-dimensional cross point memory array having M levels of memory cells disposed in cross points of N first access line layers and P second access line layers. The integrated circuit further comprises first and second sets of first access line drivers. The first set of first access line drivers is operatively coupled to apply a common first operational voltage to selected first access lines in odd first access line layers. The second set of first access line drivers is operatively coupled to apply the common first operational voltage to selected first access lines in even first access layers. A plurality of sets of second access line drivers is operatively configured to apply a second operational voltage to selected second access lines in selected second access line layers.

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

Abstract: Devices are provided for measuring and/or adjusting the distance between two opposing surfaces of a work space, such as two vertebral bodies separated by a disc space. A sizing device may include at least one distraction member, an actuator, and an actuator controller. The actuator controller is movable to move the actuator, with movement of the actuator changing the height dimension of the distraction member. The amount of movement of the actuator controller is generally linearly related to the change of the height dimension of the distraction member throughout the entire range of motion of the actuator controller. The amount of expansion force applied by the distraction member is also generally linearly related to the amount of movement of the actuator controller.