Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: A knowledge graph construction system and method are disclosed. The system generates a recommended subject entity, at least one recommended object entity, and at least one recommended relation for a piece of text data according to the text data and a plurality of triples. The system displays the recommended object entity and the recommended relation at a current paragraph of the text data according to the recommended subject entity for user to select. The system receives a confirmed message related to the recommended subject entity, a recommended object entity selected by user from the at least one recommended object entity, and a recommended relation selected by user from the at least one recommended relation. The system adds the recommended subject entity and the selected recommended object entity and recommended relation to the triples, and constructs a current knowledge graph by using the triples according to the confirmed message.

Abstract: A knowledge graph generating apparatus, method and non-transitory computer readable storage medium thereof are provided. The apparatus marks an entity-relationship of the template of goods information in the template of webpage according to the operating signal and generates an extraction rule set, wherein the template of webpage is one of multiple goods webpages and has a template format. The apparatus extracts a plurality of first product information of the first goods webpages according to the extraction rule set, wherein the first goods webpages have the template format and are selected from the goods webpages. The apparatus generates a classified goods information result through a product information classification model, wherein the product information classification model is generated based on the first product information and the entity-relationship of the template of goods information.

Abstract: An apparatus and method for verification of information are provided. The apparatus for verification of information includes a storage and a processor, wherein the storage and the processor are electrically connected with each other. The storage stores a reference knowledge graph. The processor generates a to-be-verified knowledge graph of a to-be-verified article by a knowledge graph engine. The processor generates a verified result of the to-be-verified article by comparing the to-be-verified knowledge graph and the reference knowledge graph. The knowledge graph engine may generate the reference knowledge graph by searching and labeling a plurality of related articles according to a plurality of reference articles that have been labeled.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: A knowledge graph generating apparatus, method and non-transitory computer readable storage medium thereof are provided. The apparatus marks an entity-relationship of the template of goods information in the template of webpage according to the operating signal and generates an extraction rule set, wherein the template of webpage is one of multiple goods webpages and has a template format. The apparatus extracts a plurality of first product information of the first goods webpages according to the extraction rule set, wherein the first goods webpages have the template format and are selected from the goods webpages. The apparatus generates a classified goods information result through a product information classification model, wherein the product information classification model is generated based on the first product information and the entity-relationship of the template of goods information.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.