Patents by Inventor Hsin-Yu CHANG

Hsin-Yu CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294028
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20250118594
    Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei SU, Hsin-Ping CHEN, Yung-Hsu WU, Li-Ling SU, Chan-Yu LIAO, Shao-Kuan LEE, Ting-Ya LO, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Publication number: 20250103284
    Abstract: An electronic device includes a first buffer, a second buffer, and a multiplexer. The first buffer receives and stores first data when the first buffer is not full, and performs a First-In-First-Out (FIFO) operation on the first data. The second buffer receives and stores second data when the first buffer is full, and performs the FIFO operation on the second data. The multiplexer is electrically connected between the first buffer and the second buffer. The multiplexer receives the first data from outside of the electronic device, or it receives the second data from the second buffer. A depth of the first buffer is less than that of the second buffer.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 27, 2025
    Inventors: Ming-Hung HSIEH, Pei-Lun WU, Hsin-Yu CHANG, Yu-Cheng WU
  • Publication number: 20250081255
    Abstract: The present disclosure discloses a Bluetooth communication system. A first access point apparatus of a Bluetooth access point apparatus performs periodic broadcast communication.
    Type: Application
    Filed: August 29, 2024
    Publication date: March 6, 2025
    Inventors: CHIA-CHUN HUNG, Li-Ya Huang, Hsin-Yu Chang, Yu Chiang, Po-Sheng Chiu, Yu-Hsin Lu
  • Patent number: 12238934
    Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yu Chen, Hsin-Yu Lai, Sheng-Hung Shih, Fu-Chen Chang, Kuo-Chi Tu
  • Patent number: 12219123
    Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 4, 2025
    Assignee: LIXEL INC.
    Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Hsin-You Hou, Chih-Wei Shih, Wei-An Chen, Kuan-Yu Chen
  • Publication number: 20250020852
    Abstract: A light guide plate includes a light incident surface, a first surface connected to the light incident surface, and a plurality of optical microstructures disposed on the first surface. Each optical microstructure has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction perpendicular to the first direction. The first cross-sectional profile is different from the second cross-sectional profile. The optical microstructures include a plurality of first optical microstructures and a plurality of second optical microstructures. The second cross-sectional profile of each first optical microstructure is different from the second cross-sectional profile of each second optical microstructure. A light source module including the light guide plate projects light into the light incident surface.
    Type: Application
    Filed: March 8, 2024
    Publication date: January 16, 2025
    Applicant: CM Visual Technology Corporation
    Inventors: Tsang-Chi Wang, Hsin Wen Chang, Hung Yu Lin, Yung Pin Chen
  • Patent number: 12147290
    Abstract: An example computer-implemented method is for managing a compute system with FRUs. The computer-implemented method includes receiving status information corresponding to the FRUs. The status information is collected from the FRUs in response to the compute system being powered on. The computer-implemented method also includes, in response to a predetermined condition being met, sending for each of the FRUs, one or more instructions to erase a dynamic portion of electrically erasable programmable read-only memory (EEPROM) located at a respective FRU; and sending for each of the FRUs, one or more instructions to write a portion of the status information corresponding to the respective FRU in the dynamic portion of the EEPROM at the respective FRU. Moreover, the EEPROM at each FRU includes the dynamic portion and a read-only portion.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: November 19, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Jyun-Jie Huang, Shu-Ming Chu, Hsin-Yu Chang
  • Publication number: 20240282083
    Abstract: A method for evaluating data to be used to train an object recognition model is to be implemented by a computing device. The computing device stores a plurality of training datasets respectively related to a plurality of images, and each training dataset includes a plurality of entries of training data. The method includes steps of: obtaining, for each image, at least one target area and at least one target property that are related to the image based on the entries of training data; creating, for each image, a training material that includes the image, and the at least one target area and the at least one target property both related to the image; and obtaining at least three object recognition models based on the training materials that are created respectively for the images using at least one machine learning algorithm.
    Type: Application
    Filed: September 6, 2023
    Publication date: August 22, 2024
    Inventors: Paul Yuan-Bao SHIEH, Yi-Hsuan CHEN, Thiam-Sun PANG, Chia-I CHENG, Hung-Yu CHIEN, Hsin-Yu CHANG
  • Publication number: 20240275423
    Abstract: A method for controlling the operation of a dual Bluetooth architecture of a single IC includes: after establishing a first link of a first Bluetooth circuit, performing a first group of steps; and after establishing a second link of a second Bluetooth circuit, performing a second group of steps. The first group of steps includes: determining whether the second link uses a modulation technique; when the second link uses the modulation technique, disabling the first Bluetooth circuit from using it; and when the second link does not use the modulation technique, enabling the first Bluetooth circuit to use it. The second group of steps includes: determining whether the first link uses the modulation technique; when the first link uses the modulation technique, disabling the second Bluetooth circuit from using it; and when the first link does not use the modulation technique, enabling the second Bluetooth circuit to use it.
    Type: Application
    Filed: August 11, 2023
    Publication date: August 15, 2024
    Inventors: YOU-RUNG CHOU, CHING-HER HUANG, HSIN-YU CHANG
  • Publication number: 20240272973
    Abstract: An example computer-implemented method is for managing a compute system with FRUs. The computer-implemented method includes receiving status information corresponding to the FRUs. The status information is collected from the FRUs in response to the compute system being powered on. The computer-implemented method also includes, in response to a predetermined condition being met, sending for each of the FRUs, one or more instructions to erase a dynamic portion of electrically erasable programmable read-only memory (EEPROM) located at a respective FRU; and sending for each of the FRUs, one or more instructions to write a portion of the status information corresponding to the respective FRU in the dynamic portion of the EEPROM at the respective FRU. Moreover, the EEPROM at each FRU includes the dynamic portion and a read-only portion.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 15, 2024
    Inventors: Jyun-Jie HUANG, Shu-Ming CHU, Hsin-Yu CHANG
  • Patent number: 11697993
    Abstract: A rotary engine is provided, including: a stator assembly, including an intake stator including an annular intake groove and an exhaust stator including an annular exhaust groove which define a track therebetween; a rotor, rotatably disposed between the intake and exhaust stators, including cylinders each being covered by one of the cylinder head and cylinder heads each including an intake port and an exhaust port, the intake and exhaust ports being connected to the annular intake and exhaust grooves, respectively; a shaft, inserted axially in the stator assembly and the rotor; valve mechanisms, posited on the cylinder heads respectively and each including an intake valve and an exhaust valve; pistons, received in the cylinders respectively and each including a piston rod which is movable along the track; and spark plugs, posited on the cylinder heads and exposed to interiors of the cylinders, respectively.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: July 11, 2023
    Inventors: Shih-Ho Chang, Han-Chih Chang, Hsin-Yu Chang
  • Patent number: 11406022
    Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-I Wu, Shih-Ming Lin, Pin-Hao Hu, Yu-Chung Lin, Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang
  • Patent number: 11338392
    Abstract: A cutting method for forming a chamfered corner includes a step of selecting a light pattern-adjusting module according to a pre-cut chamfer angle, a step of the light pattern-adjusting module emitting a laser beam to a substrate and thus forming a modified region extending in a thickness direction at the substrate, a step of the light pattern-adjusting module adjusting an axial energy distribution of a light pattern of the laser beam to vary an appearance of the modified region so as to form the modified region fulfilling the pre-cut chamfer angle, and a step of etching the substrate having the modified region to form a chamfered surface on the substrate by cutting the modified region from the substrate.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 24, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang, Yu-Chung Lin, Min-Kai Lee
  • Publication number: 20220141961
    Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 5, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-I Wu, Shih-Ming Lin, Pin-Hao Hu, Yu-Chung Lin, Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang
  • Patent number: 10931044
    Abstract: The disclosure relates to a board-to-board connector including a body, multiple terminals and a pair of metal fittings. The body has an accommodating recess. The terminal is disposed on the body and a portion of each of the terminals extends to the accommodating recess. The metal fittings are disposed on the body and beside the accommodating recess. The terminals are located between metal fittings. Each of the metal fittings has at least one limiting portion that extends to the accommodating recess. The limiting portion leans against a corner of the accommodating recess so that the metal fittings and the body generate a two-dimensional limitation. A board-to-board connector assembly is also provided.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Advanced Connectek Inc.
    Inventors: Ta-Teh Meng, Mei Shi, Ya-Ping Liang, Wen-Liang Men, Zheng Li, Ping Shi, Meng Liu, Bo-Wen Xu, Jia-Ying Wu, Hsin-Yu Chang
  • Publication number: 20200147729
    Abstract: A cutting method for forming a chamfered corner includes a step of selecting a light pattern-adjusting module according to a pre-cut chamfer angle, a step of the light pattern-adjusting module emitting a laser beam to a substrate and thus forming a modified region extending in a thickness direction at the substrate, a step of the light pattern-adjusting module adjusting an axial energy distribution of a light pattern of the laser beam to vary an appearance of the modified region so as to form the modified region fulfilling the pre-cut chamfer angle, and a step of etching the substrate having the modified region to form a chamfered surface on the substrate by cutting the modified region from the substrate.
    Type: Application
    Filed: February 19, 2019
    Publication date: May 14, 2020
    Inventors: HSIN-YU CHANG, FU-LUNG CHOU, CHIEN-JUNG HUANG, YU-CHUNG LIN, MIN-KAI LEE
  • Publication number: 20200136284
    Abstract: The disclosure relates to a board-to-board connector including a body, multiple terminals and a pair of metal fittings. The body has an accommodating recess. The terminal is disposed on the body and a portion of each of the terminals extends to the accommodating recess. The metal fittings are disposed on the body and beside the accommodating recess. The terminals are located between metal fittings. Each of the metal fittings has at least one limiting portion that extends to the accommodating recess. The limiting portion leans against a corner of the accommodating recess so that the metal fittings and the body generate a two-dimensional limitation. A board-to-board connector assembly is also provided.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Applicant: Advanced Connectek Inc.
    Inventors: Ta-Teh Meng, Mei Shi, Ya-Ping Liang, Wen-Liang Men, Zheng Li, Ping Shi, Meng Liu, Bo-Wen Xu, Jia-Ying Wu, Hsin-Yu Chang
  • Patent number: 9754637
    Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 5, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Hsiang-Pang Li, Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang
  • Publication number: 20170148493
    Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
    Type: Application
    Filed: July 18, 2016
    Publication date: May 25, 2017
    Inventors: Yu-Ming Chang, Hsiang-Pang Li, Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang