Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: A power element includes a substrate structure, an insulation layer, a dielectric layer, a transistor, and a plurality of zener diodes. The transistor is located in a transistor formation region of the substrate structure. The plurality of zener diodes are located in a circuit element formation region of the substrate structure and connected in series with each other. Each of the zener diodes includes a zener diode doping structure and a zener diode metal structure. The zener diode doping structure is formed on the insulation layer and is covered by the dielectric layer. The zener diode doping structure includes a P-type doped region and an N-type doped region that are in contact with each other. The zener diode metal structure is formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.

Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.

Abstract: A power element includes a substrate structure, an insulation layer, a dielectric layer, a transistor, and a plurality of zener diodes. The transistor is located in a transistor formation region of the substrate structure. The plurality of zener diodes are located in a circuit element formation region of the substrate structure and connected in series with each other. Each of the zener diodes includes a zener diode doping structure and a zener diode metal structure. The zener diode doping structure is formed on the insulation layer and is covered by the dielectric layer. The zener diode doping structure includes a P-type doped region and an N-type doped region that are in contact with each other. The zener diode metal structure is formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, trench oxide layers, semiconductor layer structures, a dielectric layer structure and a metal structure. The substrate structure includes a base layer and an epitaxial layer having a plurality of trenches. A trench depth of each trench is X1 micrometer. The doped regions are respectively formed at bottoms of the trenches. The trench oxide layers are respectively formed on inner walls of the trenches. An oxide layer thickness of each trench oxide layer is X2 micrometers. X1 and X2 conform to the following relationship: 0.05X1?X2?0.25X1. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the semiconductor layer structures. The metal structure is formed on the dielectric layer structure.

Abstract: A high-voltage metal-oxide-semiconductor field-effect transistor applied to a high-voltage range includes a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of first trenches, a plurality of second trenches, a plurality of second doped regions, and a metal layer. The epitaxial layer is disposed on the substrate and used as a drain electrode. The plurality of first doped regions are disposed in the epitaxial layer. The plurality of first trenches are disposed on the plurality of doped regions in a spaced manner. Each of the first trenches has a first trench oxide layer and a first semiconductor layer which is connected to a source electrode. The plurality of second trenches are disposed between each of the first trenches in a spaced manner. Each of the second trenches has a second trench oxide layer and a second semiconductor layer which is connected to a gate electrode.

Abstract: A high-voltage metal-oxide-semiconductor field-effect transistor applied to a high-voltage range includes a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of first trenches, a plurality of second trenches, a plurality of second doped regions, and a metal layer. The epitaxial layer is disposed on the substrate and used as a drain electrode. The plurality of first doped regions are disposed in the epitaxial layer. The plurality of first trenches are disposed on the plurality of doped regions in a spaced manner. Each of the first trenches has a first trench oxide layer and a first semiconductor layer which is connected to a source electrode. The plurality of second trenches are disposed between each of the first trenches in a spaced manner. Each of the second trenches has a second trench oxide layer and a second semiconductor layer which is connected to a gate electrode.

Abstract: A high voltage Schottky diode applied to a high voltage range includes a substrate, an epitaxy layer, doped regions, trenches and a metal layer. The epitaxy layer is disposed on the substrate. The doped regions are disposed in the epitaxy layer. The trenches are disposed on the doped regions in a spaced manner and are in the epitaxy layer. Each trench has a trench oxide layer and a semiconductor layer. Each trench oxide layer is formed on a bottom of each trench and the side of each trench. Each semiconductor layer fills each trench. The metal layer is disposed on the epitaxy layer and become a Schottky contact with the epitaxy layer. Since each depth of the plurality of trenches is micrometer-sized and there is the configuration of the trench oxide layers, this high voltage Schottky diode can operate successfully in a high voltage range.

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

Abstract: Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract: Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

Abstract: A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region.

Abstract: A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.