Patents by Inventor Hsin-Yu Lai
Hsin-Yu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128531Abstract: The present disclosure discloses a method for recycling all types of lithium batteries. First, the lithium battery waste is acid-leached to obtain a solution containing most of metal ions. After filtering, the solution is separated from the remaining solids, and then the obtained solution is subjected to separate precipitation many times. After separately adjusting the pH value of the solution many times, adding precipitants with a high selectivity ratio, and matching with filtration and separation reaction, all ions in the lithium battery waste are sequentially precipitated in forms of iron phosphate (FePO4), aluminum hydroxide (Al(OH)3), manganese oxide (MnO2), dicobalt trioxide (cobalt oxide, Co2O3), nickel hydroxide (Ni(OH)2), and lithium carbonate (Li2CO3).Type: ApplicationFiled: September 24, 2023Publication date: April 18, 2024Applicant: Cleanaway Company LimitedInventors: CHIH-HUANG LAI, HSIN-FANG CHANG, TZU-MIN CHENG, YUNG-FA YANG, TSUNG-TIEN CHEN, ZHENG-YU CHENG, CHI-YUNG CHANG
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Publication number: 20240071936Abstract: Disclosed are an interposer substrate, a package structure and a manufacturing method of a package structure. In one embodiment, the interposer substrate includes a substrate, a bridge device in the substrate, a memory in the substrate and beside the bridge device and a through substrate via in the substrate and beside the bridge device and the memory.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Ling, Hsin-Yu LAI, Katherine H CHIANG, Chung-Te Lin
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Patent number: 11916127Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: GrantFiled: June 16, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Publication number: 20240021700Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: ApplicationFiled: August 8, 2023Publication date: January 18, 2024Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Publication number: 20230065132Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yu CHEN, Hsin-Yu LAI, Sheng-Hung SHIH, Fu-Chen CHANG, Kuo-Chi TU
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Publication number: 20230008075Abstract: A capacitor structure, a method for manufacturing a capacitor structure and a method for operating a capacitor structure are provided. The capacitor structure includes a first electrode and a second electrode; a dielectric layer between the first electrode and the second electrode; and an oxygen donor layer between the dielectric layer and the first electrode. An oxygen concentration of the oxygen donor layer increases along a thickness direction from a first surface proximal to the dielectric layer to a second surface proximal to the first electrode.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Inventors: HSIN-YU LAI, KATHERINE H. CHIANG
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Publication number: 20230011756Abstract: A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures.Type: ApplicationFiled: March 10, 2022Publication date: January 12, 2023Inventors: Cheng-Yi WU, Katherine H. CHIANG, Chung-Te LIN, Hsin-Yu LAI, Yun-Feng KAO
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Publication number: 20220406916Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Publication number: 20220359645Abstract: A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.Type: ApplicationFiled: September 10, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yu LAI, Katherine H. CHIANG
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Patent number: 8759096Abstract: Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues).Type: GrantFiled: May 7, 2010Date of Patent: June 24, 2014Assignee: National Tsing Hua UniversityInventors: Chen-Wei Wu, Cheng-Hsien Liu, Chau-Ting Yeh, Hui-Ling Lin, Hsin-Yu Lai, Tzu-Chi Yu
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Publication number: 20100216244Abstract: Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues).Type: ApplicationFiled: May 7, 2010Publication date: August 26, 2010Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Chen-Wei Wu, Cheng-Hsien Liu, Chau-Ting Yeh, Hui-Ling Lin, Hsin-Yu Lai, Tzu-Chi Yu