Patents by Inventor HSIN YU LI

HSIN YU LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128152
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20240021493
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20240014097
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20230317668
    Abstract: Embodiments herein relate to systems, apparatuses, or processes that include barriers, which may be referred to as flow stops, to modulate, or control, the speed of flow of an underfill between the substrate and another object on the substrate, for example one or more dies coupled with the substrate. Moderating the speed of flow of the underfill reduces the number of voids in the underfill after curing. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Ziyin LIN, Wei LI, Jingyi HUANG, Hsin-Yu LI
  • Publication number: 20210343677
    Abstract: Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Frederick W. Atadana, Taylor William Gaines, Edvin Cetegen, Wei Li, Hsin-Yu Li, Tony Dambrauskas
  • Publication number: 20210066155
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20200006169
    Abstract: A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: William WARREN, Taylor GAINES, Frederick ATADANA, Edvin CETEGEN, Vipul MEHTA, Hsin-Yu LI, Yuying WEI, Yang GUO, Ren ZHANG
  • Publication number: 20160343591
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen-Givoni, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Patent number: 9431274
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Publication number: 20140177149
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Publication number: 20140162950
    Abstract: The present invention provides a method for inhibiting peritoneal metastasis caused by gastric cancer cells in a subject in need thereof comprising administering to the subject a pharmaceutically effective amount of a connective tissue growth factor (CTGF), wherein the CTGF binds to an integrin ?3?1 of the gastric cancer cells. The present invention also provides a method for predicting peritoneal metastasis caused by gastric cancer cells in a subject comprising providing a peritoneal tissue from the subject; measuring a first expression amount of a connective tissue growth factor (CTGF) from the peritoneal tissue; and comparing the first expression amount to a reference expression amount of the CTGF from a non-peritoneal metastasis gastric cancer tissue.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Cheng-Chi Chang, Chiung-Nien Chen, Hsin-Yu Li, Min-Liang Kuo
  • Publication number: 20030157414
    Abstract: A holographic recording medium showing little or no shrinkage after exposure comprises an acid generator capable of producing an acid upon exposure to actinic radiation; a binder; a difunctional epoxide monomer or oligomer; and a polyfunctional (i.e., tri- or higher functional) epoxide monomer or oligomer, the difunctional and polyfunctional epoxide monomers or oligomers being capable of undergoing cationic polymerization initiated by the acid produced from the acid generator. The medium is especially useful for holographic data storage applications.
    Type: Application
    Filed: November 13, 1997
    Publication date: August 21, 2003
    Inventors: PRADEEP K. DHAL, RICHARD T. INGWALL, ERIC S. KOLB, HSIN YU LI, DAVID A. WALDMAN