Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.