Patents by Inventor Hsin Yuan Yu
Hsin Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240407159Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.Type: ApplicationFiled: May 31, 2023Publication date: December 5, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Ya-Chin King, Chrong Lin, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, May-Be Chen, Hsin-Yuan Yu
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Publication number: 20240355388Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
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Publication number: 20240332282Abstract: A device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of nanostructures disposed in a plurality of first semiconductor layers and a gate structure wrapping around the nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implant region extends through the plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed between respective vertically neighboring pairs of the plurality of first semiconductor layers. A backside interconnect structure is electrically connected to a source/drain region of the nanostructure device.Type: ApplicationFiled: April 3, 2023Publication date: October 3, 2024Inventors: Hsin-Yuan YU, Ming-Shuan LI, Wun-Jie LIN
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Patent number: 12051466Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: GrantFiled: April 17, 2023Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
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Publication number: 20230326521Abstract: A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der CHIH, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Hsin-Yuan YU, Chrong Jung LIN, Ya-Chin KING
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Publication number: 20230292533Abstract: A high efficiency embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer, a first memory transistor and a second memory transistor. The select transistor is disposed on the semiconductor substrate and includes a select gate structure, a drain region and a source region. The metal layer is connected to the drain region. The first memory transistor includes a first gate structure, a first electrode region and a first memristor. The second memory transistor includes a second gate structure, a second electrode region and a second memristor. The second electrode region and the first electrode region are connected to each other and form a connection region, which is connected to the metal layer. The first memristor is formed between the first gate structure and the connection region, and the second memristor is formed between the second gate structure and the connection region.Type: ApplicationFiled: July 19, 2022Publication date: September 14, 2023Inventors: Ya-Chin KING, Hsin-Yuan YU, Chrong-Jung LIN
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Publication number: 20230289577Abstract: A high density embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region.Type: ApplicationFiled: July 19, 2022Publication date: September 14, 2023Inventors: Ya-Chin KING, Hsin-Yuan YU, Chrong-Jung LIN
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Publication number: 20230253040Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, May-Be Chen, Ya-Chin King, Wen Zhang Lin, Chrong Lin, Hsin-Yuan Yu
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Patent number: 11646079Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: GrantFiled: June 3, 2021Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Maybe Chen, Yun-Sheng Chen, Wen Zhang Lin, Jonathan Tsung-Yung Chang, Chrong Jung Lin, Ya-Chin King, Hsin-Yuan Yu
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Publication number: 20220068378Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: ApplicationFiled: June 3, 2021Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Maybe Chen, Yun-Sheng Chen, Wen Zhang Lin, Jonathan Tsung-Yung Chang, Chrong Jung Lin, Ya-Chin King, Hsin-Yuan Yu
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Publication number: 20100062816Abstract: An improved mobile phone protective cover includes a plastic plate spread open and cut according to the shape of a mobile phone, and a lining and an external decorative element covered onto inner and outer layers of the plastic plate respectively. The plastic plate with the lining and the external decorative element includes a wing portion formed according to the shape of the mobile phone, and the wing portions are formed by bending the latch portions. The latch portions are fixed and combined with the periphery of the mobile phone directly and securely, and the protective cover can be combined integrally with the mobile phone in a simple and easy way without occupying much space, and achieve the purpose and effect of protecting the mobile phone.Type: ApplicationFiled: August 17, 2009Publication date: March 11, 2010Inventor: Hsin Yuan Yu