Patents by Inventor Hsin-Yun Hsu
Hsin-Yun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021729Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: Chun-Neng Lin, Ming-Hsi Yeh, Hung-Chin Chung, Hsin-Yun Hsu
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Patent number: 11830742Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: June 29, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Publication number: 20230317457Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
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Patent number: 11710638Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.Type: GrantFiled: May 28, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
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Publication number: 20220328683Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chun-Neng Lin, Ming-Hsi Yeh, Hung-Chin Chung, Hsin-Yun Hsu
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Publication number: 20220328309Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 11380542Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: September 4, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 11380793Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.Type: GrantFiled: July 31, 2019Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Neng Lin, Ming-Hsi Yeh, Hung-Chin Chung, Hsin-Yun Hsu
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Patent number: 11201227Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.Type: GrantFiled: April 27, 2018Date of Patent: December 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yun Hsu, Hsiao-Kuan Wei
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Patent number: 11145747Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.Type: GrantFiled: February 22, 2018Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yun Hsu, Hsiao-Kuan Wei
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Publication number: 20210287905Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
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Patent number: 11024505Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.Type: GrantFiled: November 29, 2018Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
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Publication number: 20210036145Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Chun-Neng Lin, Ming-Hsi Yeh, Hung-Chin Chung, Hsin-Yun Hsu
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Publication number: 20200402795Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 10854459Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.Type: GrantFiled: November 28, 2017Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
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Publication number: 20200369486Abstract: A flexible substrate adjusting device includes a substrate transmission mechanism, a pressure roller, and a force applying assembly. The substrate transmission mechanism has a transmission direction for carrying a first surface of a flexible substrate thereon. The pressure roller is disposed on at least one side of a second surface of the flexible substrate in a non-transmission direction. The force applying assembly is connected to the pressure roller and provides the pressure roller with a pressure to the flexible substrate, wherein when the flexible substrate moves in the transmission direction, the pressure roller generates a friction force in the non-transmission direction with the flexible substrate to adjust flatness or position of the flexible substrate.Type: ApplicationFiled: December 26, 2019Publication date: November 26, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Hsin HUANG, Yu-Lin HSU, Chien-Hung LIN, Hsin-Yun HSU
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Patent number: 10790142Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: January 25, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Hsiao-Kuan Wei, Hung-Wen Su, Pei-Hsuan Lee, Hsin-Yun Hsu, Jui-Fen Chien
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Patent number: 10770288Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: November 30, 2018Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Publication number: 20190334007Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yun HSU, Hsiao-Kuan WEI
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Patent number: 10308461Abstract: A roller assembly for transporting a substrate includes a step roller and a plurality of first auxiliary rollers. The step roller includes a main roller, and a pair of edge rollers sleeved on the main roller and located on two opposite ends of the main roller, respectively. The plurality of first auxiliary rollers are disposed on two opposite sides of the step roller, respectively. A first film forms a closed loop through the first film being rolled on the plurality of first auxiliary rollers and the step roller cyclically. A method using the same is also provided.Type: GrantFiled: November 25, 2016Date of Patent: June 4, 2019Assignee: Industrial Technology Research InstituteInventors: Kuo-Hsin Huang, Chao-Feng Sung, Yu-Lin Hsu, Hsin-Yun Hsu