Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: An electronic apparatus includes a main circuit board, a seat body, a detachable element and a detection element. The seat body is disposed on the main circuit board and includes an opening and a conductive structure located in the opening. The detection element is disposed on the detachable element and includes an elastic conductive member. The elastic conductive member is adapted to extend into the opening, apply an elastic force to the seat body in the opening, and electrically contact the conductive structure. The main circuit board is adapted to determine that the seat body and the detection element are in a first state or a second state. The first state includes that the elastic conductive member electrically contacts the conductive structure. The second state includes that the elastic conductive member is separated from the conductive structure.

Abstract: A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.

Abstract: A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.

Abstract: A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.

Abstract: A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.