Abstract: The write circuit for SRAM memories of this invention includes on each column select line B1,B1' a N-type transistor (N1, N2) which is utilized to drive the voltage on one of the column select lines to V.sub.cc -V.sub.t. A pull-up circuit circuit is also provided with each column select line B1, B1'which includes a P-type transistor (P1,P2) which is coupled to the supply V.sub.cc. This circuit raises the voltage which appears between the two column select lines B1, B1' to V.sub.cc which is used to write data to a SRAM cell 10, 12 disposed therebetween.

Abstract: A tristateable sense amplifier, for driving a bus directly with minimal size devices, includes a control transistor coupled to a reference voltage terminal and having a control electrode receiving a first control signal. A first series circuit includes a first transistor of a first channel type and a second transistor of opposite channel type coupled between the control transistor and a supply voltage terminal. A control electrode of the second transistor receives a first input signal and the second transistor generates a first output signal. A second series circuit includes a third transistor of the first channel type and a found transistor of the opposite channel type coupled between the control transistor and the supply terminal. A second input signal is coupled to the control electrode of the fourth transistor.

Abstract: A floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage, serves to clamp electrostatic discharge voltages to a low voltage level, thereby minimizing thermal power dissipation within the thin semiconductor layer of semiconductor-on-insulator circuits.

Abstract: A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor.

Abstract: A silicon-on-insulator MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor.