Abstract: A method for resetting a memory in the computer system includes turning on the computer system, and a memory controller of the computer system executing a boot code to initialize the memory. After the memory controller executes the boot code, the memory controller updates a programmable initialization code according to the boot code to generate an updated programmable initialization code. After resetting the computer system, the memory controller executes the updated programmable initialization code to restore the memory back to a default state. After the memory is restored to the default state, the memory controller executes the boot code to initialize the memory again. After the memory is initialized, the memory controller controls the memory to perform a normal operation.

Abstract: A method for resetting a memory in the computer system includes turning on the computer system, and a memory controller of the computer system executing a boot code to initialize the memory. After the memory controller executes the boot code, the memory controller updates a programmable initialization code according to the boot code to generate an updated programmable initialization code. After resetting the computer system, the memory controller executes the updated programmable initialization code to restore the memory back to a default state. After the memory is restored to the default state, the memory controller executes the boot code to initialize the memory again. After the memory is initialized, the memory controller controls the memory to perform a normal operation.

Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

Abstract: The present technology is directed to a method for accessing a memory device in response to read requests is described. The method comprises, in response to a first request, composing a first read sequence using a command protocol of the memory device. The first read sequence includes a command code and a starting physical address. Upon receipt of a second request, the method determines a starting physical address of a second read sequence according to the command protocol of the memory device. If the starting physical address of the second read sequence is sequential to an ending physical address of the first read sequence, then the method composes the second read sequence using the command protocol without a command code, else the method composes the second read sequence using the command protocol with a read command.

Abstract: The present technology is directed to a method for accessing a memory device in response to read requests is described. The method comprises, in response to a first request, composing a first read sequence using a command protocol of the memory device. The first read sequence includes a command code and a starting physical address. Upon receipt of a second request, the method determines a starting physical address of a second read sequence according to the command protocol of the memory device. If the starting physical address of the second read sequence is sequential to an ending physical address of the first read sequence, then the method composes the second read sequence using the command protocol without a command code, else the method composes the second read sequence using the command protocol with a read command.

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.