Patents by Inventor Hsing-Chi Chen
Hsing-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12568667Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: GrantFiled: April 11, 2022Date of Patent: March 3, 2026Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Publication number: 20250343070Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: ApplicationFiled: July 16, 2025Publication date: November 6, 2025Inventors: Soon-Kang HUANG, Hsing-Chi CHEN
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Publication number: 20240395602Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: ApplicationFiled: July 29, 2024Publication date: November 28, 2024Inventors: Soon-Kang Huang, Hsing-Chi Chen
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Patent number: 12020980Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: GrantFiled: January 13, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Soon-Kang Huang, Hsing-Chi Chen
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Publication number: 20230386895Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Soon-Kang HUANG, Hsing-Chi CHEN
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Publication number: 20230016445Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: ApplicationFiled: January 13, 2022Publication date: January 19, 2023Inventors: Soon-Kang HUANG, Hsing-Chi CHEN
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Publication number: 20220238656Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Patent number: 11366710Abstract: A system and method for shortening the system management mode when a fault occurs in hardware component in a computer system is disclosed. The computer system has hardware components that may have faults. Notification of an error in one of the hardware components is received through RAS silicon on a processing unit. The error is detected from the hardware component by a system management interrupt handler executed by a bootstrap processor core. The error data is logged into a system error log via a system control interrupt handler executed by the processing unit. The system management mode is avoided during the logging of the error data. This prevents other processor cores being suspended from the system management mode.Type: GrantFiled: February 23, 2021Date of Patent: June 21, 2022Assignee: QUANTA COMPUTER INC.Inventors: Ming-Hung Hung, Hsing-Chi Chen, Yan-Ting Jiang
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Patent number: 11302782Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: GrantFiled: May 4, 2020Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Publication number: 20200266274Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Patent number: 10644116Abstract: A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.Type: GrantFiled: February 6, 2014Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Publication number: 20150221509Abstract: A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.Type: ApplicationFiled: February 6, 2014Publication date: August 6, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng