Abstract: A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal.

Abstract: A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal.

Abstract: A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver.

Abstract: A controller driver for driving a display panel is provided. The controller driver comprises a timing control circuit, a data memory unit, a data selection unit and a data line driver circuit. The data memory unit stores image data. The data selection unit coupled to the data memory unit outputs the image data provided from the data memory unit as a display data, or generates the display data in accordance with a command or test patterns provided from an external processor. The data line driver circuit is coupled to the timing control circuit and the data selection unit. The data line driver circuit receives the display data from the data selection unit, and outputs corresponding grayscale voltages according to the control signal outputted from the timing control circuit.

Abstract: A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal.

Abstract: A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j?PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.

Abstract: A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal.

Abstract: A controller driver for driving a display panel is provided. The controller driver comprises a timing control circuit, a data memory unit, a data selection unit and a data line driver circuit. The data memory unit stores image data. The data selection unit coupled to the data memory unit outputs the image data provided from the data memory unit as a display data, or generates the display data in accordance with a command or test patterns provided from an external processor. The data line driver circuit is coupled to the timing control circuit and the data selection unit. The data line driver circuit receives the display data from the data selection unit, and outputs corresponding grayscale voltages according to the control signal outputted from the timing control circuit.

Abstract: A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver.

Abstract: A display controller driver and a testing method therewith are provided. The display controller driver includes a timing control circuit, an image data memory, a data line driving circuit and a scan line driving circuit. The testing method includes controlling the scan line driving circuit by a control signal in a test operation mode, wherein the control signal is generated by an external test platform. The scan line driving circuit is tested and measured in accordance with a test pattern of the control signal.

Abstract: A motion estimation circuit and a motion estimation processing element are provided. The latch module in the motion estimation circuit has n pieces of m-stage shift registers. Each shift register receives a current block data and transmits the received current block data to next stage according to a timing. The processing module has a plurality of processing elements (PEs), which are divided into (m+1) groups. The PEs of the i-th group receive the left search window data and the right search window data and are coupled to the input ends and the output ends of the i-th stage of latches, wherein 0<i?m. Each PE compares the similarity degree between the corresponding candidate block in the search window and the current block and outputs the processed result, respectively. The comparing unit receives and compares the processed results for outputting a first comparison result.

Abstract: The present invention provides a motion estimation circuit and an operating method thereof. The motion estimation circuit includes processing elements PEm (?n?m?n, n represents a search range), data latches FFk (?n<k?n) and selection circuits MUXh (?1?h?1). The processing element receives a current block data and the corresponded block data in a search window and performs a comparison operation on the two block data. The output-end of FFk is coupled to an input-end of FFk+1 and a first input-end of PEk. The output-end of MUXh is coupled to a second input-end of PEh. Wherein, each 4×4-pixel sub block of the current block is input into PE?n and FF?(n?1), the left sector of the sub-search-window SW? is input into the second input-ends of PE?n˜PE?2 and the first input-end of MUXh, and the right sector of the sub-search-window SW? is input into the second input-ends of PE2˜PEn and MUXh.

Abstract: A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory.

Abstract: A motion estimation circuit and a motion estimation processing element are provided. The latch module in the motion estimation circuit has n pieces of m-stage shift registers. Each shift register receives a current block data and transmits the received current block data to next stage according to a timing. The processing module has a plurality of processing elements (PEs), which are divided into (m+l) groups. The PEs of the i-th group receive the left search window data and the right search window data and are coupled to the input ends and the output ends of the i-th stage of latches, wherein 0<i?m. Each PE compares the similarity degree between the corresponding candidate block in the search window and the current block and outputs the processed result, respectively. The comparing unit receives and compares the processed results for outputting a first comparison result.

Abstract: The present invention provides a motion estimation circuit and an operating method thereof. The motion estimation circuit includes processing elements PEm (?n?m?n, n represents a search range), data latches FFk (?n<k?n) and selection circuits MUXh (?1?h?1). The processing element receives a current block data and the corresponded block data in a search window and performs a comparison operation on the two block data. The output-end of FFk is coupled to an input-end of FFk+1 and a first input-end of PEk. The output-end of MUXh is coupled to a second input-end of PEh. Wherein, each 4×4-pixel sub block of the current block is input into PE?n and FF?(n?1), the left sector of the sub-search-window SW? is input into the second input-ends of PE?n˜PE?2 and the first input-end of MUXh, and the right sector of the sub-search-window SW? is input into the second input-ends of PE2˜PEn and MUXh.

Abstract: A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j?PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.